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| ZL50415 Unmanaged 16-Port 10/100M Ethernet Switch Data Sheet Features * * Integrated Single-Chip 10/100 Mbps Ethernet Switch 16 10/100 Mbps Autosensing, Fast Ethernet Ports with RMII or Serial Interface (7WS). Each port can independently use one of the two interfaces. Serial CPU interface for configuration Supports one Frame Buffer Memory domain with SRAM at 100 MHz Supports SRAM domain memory size 1 MB, or 2 MB Applies centralized shared memory architecture Up to 64K MAC addresses Maximum throughput is 1.6 Gbps non-blocking High performance packet forwarding (4.762M packets per second) at full wire speed Full Duplex Ethernet IEEE 802.3x Flow Control Backpressure flow control for Half Duplex ports Supports Ethernet multicasting and broadcasting and flooding control Supports per-system option to enable flow control for best effort frames even on QoS-enabled ports Load sharing among trunked ports can be based on source MAC and/or destination MAC. Ordering Information ZL50415/GKC 553 Pin HSBGA February 2003 * * * * * * * * * * * * -40C to 85C * * * * * Port Mirroring to a dedicated mirroring port Full set of LED signals provided by a serial interface 2 port trunking groups with up to 4 10/100 ports per group Built-In Self Test for internal and external SRAM Traffic Classification * 4 transmission priorities for Fast Ethernet ports with 2 dropping levels * Classification based on: - Port based priority - VLAN Priority field in VLAN tagged frame - DS/TOS field in IP packet - UDP/TCP logical ports: 8 hard-wired and 8 programmable ports, including one programmable range * The precedence of the above classifications is programmable. VLAN 1 MCT Frame Data Buffer A SRAM (1M / 2M) FDB Interface LED FCB Frame Engine Search Engine MCT Link 16 x 10 /100 RMII Ports 0 - 15 Management Module Parallel / Serial Figure 1 - ZL50415 System Block Diagram 1 ZL50415 * QoS Support Data Sheet * Supports IEEE 802.1p/Q Quality of Service with 4 transmission priority queues with delay bounded, strict priority, and WFQ service disciplines * Provides 2 levels of dropping precedence with WRED mechanism * User controls the WRED thresholds. * Buffer management: per class and per port buffer reservations * Port-based priority: VLAN priority in a tagged frame can be overwritten by the priority of Port VLAN ID. * * * * Hardware auto-negotiation through serial management interface (MDIO) for Ethernet ports Built-in reset logic triggered by system malfunction I2C EEPROM for configuration 553 BGA package Description The ZL50415 is a high density, low cost, high performance, non-blocking Ethernet switch chip. A single chip provides 16 ports at 10/100 Mbps, for unmanaged switch applications. The chip supports up to 64K MAC addresses. The centralized shared memory architecture permits a very high performance packet forwarding rate at up to 3.571M packets per second at full wire speed. The chip is optimized to provide low-cost, high-performance workgroup switching. The Frame Buffer Memory domains utilize cost-effective, high-performance synchronous SRAM with aggregate bandwidth of 6.4 Gbps to support full wire speed on all ports simultaneously. With delay bounded, strict priority, and/or WFQ transmission scheduling, and WRED dropping schemes, the ZL50415 provides powerful QoS functions for various multimedia and mission-critical applications. The chip provides 4 transmission priorities and 2 levels of dropping precedence. Each packet is assigned a transmission priority and dropping precedence based on the VLAN priority field in a VLAN tagged frame, or the DS/TOS field, and UDP/TCP logical port fields in IP packets. The ZL50415 recognizes a total of 16 UDP/TCP logical ports, 8 hard-wired and 8 programmable (including one programmable range). The ZL50415 supports 2 groups of port trunking/load sharing. Each 10/100 group can contain up to 4 ports. Port trunking/load sharing can be used to group ports between interlinked switches to increase the effective network bandwidth. In half-duplex mode, all ports support backpressure flow control, to minimize the risk of losing data during long activity bursts. In full-duplex mode, IEEE 802.3x flow control is provided. The ZL50415 also supports a persystem option to enable flow control for best effort frames, even on QoS-enabled ports. The ZL50415 is fabricated using 0.25 micron technology. Inputs, however, are 3.3 V tolerant, and the outputs are capable of directly interfacing to LVTTL levels. The ZL50415 is packaged in a 553-pin Ball Grid Array package. 2 Zarlink Semiconductor Inc. Data Sheet Table of Contents ZL50415 1.0 Block Functionality.......................................................................................................... 13 1.1 Frame Data Buffer (FDB) Interfaces ..........................................................................................................13 1.2 10/100 MAC Module (RMAC) ....................................................................................................................13 1.3 Configuration Interface Module..................................................................................................................13 1.4 Frame Engine ...........................................................................................................................................13 1.5 Search Engine ..........................................................................................................................................13 1.6 LED Interface .............................................................................................................................................13 1.7 Internal Memory ........................................................................................................................................13 2.0 System Configuration ..................................................................................................... 14 2.1 Configuration Mode....................................................................................................................................14 2.2 I2C Interface ..............................................................................................................................................14 2.2.1 Start Condition..................................................................................................................................14 2.2.2 Address ............................................................................................................................................14 2.2.3 Data Direction...................................................................................................................................14 2.2.4 Acknowledgment ..............................................................................................................................14 2.2.5 Data ..................................................................................................................................................14 2.2.6 Stop Condition ..................................................................................................................................14 2.3 Synchronous Serial Interface.....................................................................................................................15 2.3.1 Write Command................................................................................................................................15 2.3.2 Read Command ...............................................................................................................................15 3.0 ZL50415 Data Forwarding Protocol ............................................................................... 16 3.1 Unicast Data Frame Forwarding ................................................................................................................16 3.2 Multicast Data Frame Forwarding .............................................................................................................16 4.0 Memory Interface ............................................................................................................. 17 4.1 Overview ...................................................................................................................................................17 4.2 Detailed Memory Information.....................................................................................................................17 4.3 Memory Requirements...............................................................................................................................17 5.0 Search Engine.................................................................................................................. 18 5.1 Search Engine Overview ..........................................................................................................................18 5.2 Basic Flow..................................................................................................................................................18 5.3 Search, Learning, and Aging .....................................................................................................................18 5.3.1 MAC Search .....................................................................................................................................18 5.3.2 Learning............................................................................................................................................18 5.3.3 Aging ................................................................................................................................................19 5.4 Quality of Service.......................................................................................................................................19 5.5 Priority Classification Rule .........................................................................................................................20 5.6 Port Based VLAN.......................................................................................................................................20 5.7 Memory Configurations..............................................................................................................................21 6.0 Frame Engine ................................................................................................................... 23 6.1 Data Forwarding Summary .......................................................................................................................23 6.2 Frame Engine Details ................................................................................................................................23 6.2.1 FCB Manager ...................................................................................................................................23 6.2.2 Rx Interface ......................................................................................................................................24 6.2.3 RxDMA .............................................................................................................................................24 6.2.4 TxQ Manager....................................................................................................................................24 6.3 Port Control................................................................................................................................................24 6.4 TxDMA .......................................................................................................................................................24 7.0 Quality of Service and Flow Control .............................................................................. 24 7.1 Model ........................................................................................................................................................24 7.2 Four QoS Configurations ...........................................................................................................................26 7.3 Delay Bound ..............................................................................................................................................26 7.4 Strict Priority and Best Effort......................................................................................................................26 Zarlink Semiconductor Inc. iii ZL50415 Table of Contents Data Sheet 7.5 Weighted Fair Queuing ..............................................................................................................................27 7.6 WRED Drop Threshold Management Support.......................................................................................... 27 7.7 Buffer Management ...................................................................................................................................28 7.7.1 Dropping When Buffers Are Scarce .................................................................................................29 7.8 ZL50415 Flow Control Basics ....................................................................................................................29 7.8.1 Unicast Flow Control ........................................................................................................................30 7.8.2 Multicast Flow Control ......................................................................................................................30 7.9 Mapping to IETF Diffserv Classes .............................................................................................................30 8.0 Port Trunking ................................................................................................................... 31 8.1 Features and Restrictions .........................................................................................................................31 8.2 Unicast Packet Forwarding .......................................................................................................................31 8.3 Multicast Packet Forwarding......................................................................................................................31 8.4 Trunking .....................................................................................................................................................31 9.0 Port Mirroring................................................................................................................... 32 9.1 Port Mirroring Features .............................................................................................................................32 9.2 Setting Registers for Port Mirroring............................................................................................................32 10.0 GPSI (7WS) Interface ..................................................................................................... 32 10.1 GPSI connection ......................................................................................................................................32 10.2 SCAN LINK and SCAN COL interface.....................................................................................................33 11.0 LED Interface.................................................................................................................. 34 11.1 LED Interface Introduction ......................................................................................................................34 11.2 Port Status ..............................................................................................................................................34 11.3 LED Interface Timing Diagram.................................................................................................................35 12.0 Register Definition......................................................................................................... 36 12.1 ZL50415 Register Description .................................................................................................................36 12.2 Group 0 Address MAC Ports Group ........................................................................................................39 12.2.1 ECR1Pn: Port N Control Register ..................................................................................................39 12.2.2 ECR2Pn: Port N Control Register ..................................................................................................40 12.3 Group 1 Address VLAN Group ................................................................................................................41 12.3.1 AVTCL - VLAN Type Code Register Low ......................................................................................41 12.3.2 AVTCH - VLAN Type Code Register High.....................................................................................41 12.3.3 PVMAP00_0 - Port 00 Configuration Register 0............................................................................41 12.3.4 PVMAP00_1 - Port 00 Configuration Register 1............................................................................41 12.3.5 PVMAP00_3 - Port 00 Configuration Register 3............................................................................42 12.4 Port Configuration Register......................................................................................................................42 12.4.1 PVMODE ........................................................................................................................................43 12.4.2 TRUNK0_MODE- Trunk group 0 mode .........................................................................................43 12.4.3 TRUNK1_MODE - Trunk group 1 mode ........................................................................................44 12.4.4 TX_AGE - Tx Queue Aging timer ..................................................................................................44 12.5 Group 4 Address Search Engine Group ..................................................................................................44 12.5.1 AGETIME_LOW - MAC address aging time Low ..........................................................................44 12.5.2 AGETIME_HIGH -MAC address aging time High..........................................................................44 12.5.3 SE_OPMODE - Search Engine Operation Mode ..........................................................................45 12.6 Group 5 Address Buffer Control/QOS Group...........................................................................................45 12.6.1 FCBAT - FCB Aging Timer ............................................................................................................45 12.6.2 QOSC - QOS Control ....................................................................................................................45 12.6.3 FCR - Flooding Control Register ...................................................................................................46 12.6.4 AVPML - VLAN Priority Map..........................................................................................................47 12.6.5 AVPMM - VLAN Priority Map.........................................................................................................47 12.6.6 AVPMH - VLAN Priority Map .........................................................................................................47 12.6.7 TOSPML - TOS Priority Map .........................................................................................................48 12.6.8 TOSPMM - TOS Priority Map ........................................................................................................48 iv Zarlink Semiconductor Inc. Data Sheet Table of Contents ZL50415 12.6.9 TOSPMH - TOS Priority Map.........................................................................................................49 12.6.10 AVDM - VLAN Discard Map.........................................................................................................49 12.6.11 TOSDML - TOS Discard Map ......................................................................................................50 12.6.12 BMRC - Broadcast/Multicast Rate Control ...................................................................................50 12.6.13 UCC - Unicast Congestion Control ..............................................................................................51 12.6.14 MCC - Multicast Congestion Control ...........................................................................................51 12.6.15 PR100 - Port Reservation for 10/100 ports..................................................................................52 12.6.16 SFCB - Share FCB Size ..............................................................................................................52 12.6.17 C2RS - Class 2 Reserve Size......................................................................................................52 12.6.18 C3RS - Class 3 Reserve Size......................................................................................................53 12.6.19 C4RS - Class 4 Reserve Size......................................................................................................53 12.6.20 C5RS - Class 5 Reserve Size......................................................................................................53 12.6.21 C6RS - Class 6 Reserve Size......................................................................................................53 12.6.22 C7RS - Class 7 Reserve Size......................................................................................................53 12.6.23 Classes Byte Limit Set 0...............................................................................................................54 12.6.24 Classes Byte Limit Set 1...............................................................................................................54 12.6.25 Classes Byte Limit Set 2...............................................................................................................54 12.6.26 Classes Byte Limit Set 3...............................................................................................................54 12.6.27 Classes WFQ Credit Set 0 ...........................................................................................................55 12.6.28 Classes WFQ Credit Set 1 ...........................................................................................................55 12.6.29 Classes WFQ Credit Set 2 ...........................................................................................................55 12.6.30 Classes WFQ Credit Set 3 ...........................................................................................................56 12.6.31 RDRC0 - WRED Rate Control 0 ..................................................................................................56 12.6.32 RDRC1 - WRED Rate Control 1 ..................................................................................................56 12.6.33 User Defined Logical Ports and Well Known Ports ......................................................................57 12.7 Group 6 Address MISC Group.................................................................................................................61 12.7.1 MII_OP0 - MII Register Option 0 ...................................................................................................61 12.7.2 MII_OP1 - MII Register Option 1 ...................................................................................................61 12.7.3 FEN - Feature Register..................................................................................................................62 12.7.4 MIIC0 - MII Command Register 0 ..................................................................................................62 12.7.5 MIIC1 - MII Command Register 1 ..................................................................................................62 12.7.6 MIIC2 - MII Command Register 2 ..................................................................................................63 12.7.7 MIC3 - MII Command Register 3 ...................................................................................................63 12.7.8 MIID0 - MII Data Register 0 ...........................................................................................................63 12.7.9 MIID1 - MII Data Register 1 ...........................................................................................................63 12.7.10 LED Mode - LED Control .............................................................................................................64 12.7.11 CHECKSUM - EEPROM Checksum ............................................................................................64 12.8 Group 7 Address Port Mirroring Group ...................................................................................................65 12.8.1 MIRROR1_SRC - Port Mirror source port .....................................................................................65 12.8.2 MIRROR1_DEST - Port Mirror destination ....................................................................................65 12.8.3 MIRROR2_SRC - Port Mirror source port .....................................................................................65 12.8.4 MIRROR2_DEST - Port Mirror destination ....................................................................................66 12.9 Group F Address CPU Access Group .....................................................................................................66 12.9.1 GCR-Global Control Register .........................................................................................................66 12.9.2 DCR-Device Status and Signature Register...................................................................................67 12.9.3 DCR1-Chip status...........................................................................................................................67 12.9.4 DPST - Device Port Status Register..............................................................................................68 12.9.5 DTST - Data read back register.....................................................................................................69 12.9.6 PLLCR - PLL Control Register .......................................................................................................69 12.9.7 LCLK - LA_CLK delay from internal OE_CLK ................................................................................69 12.9.8 OECLK - Internal OE_CLK delay from SCLK.................................................................................70 12.9.9 DA - DA Register ...........................................................................................................................70 13.0 BGA and Ball Signal Descriptions ............................................................................... 71 13.1 BGA Views (TOP - View) .........................................................................................................................71 Zarlink Semiconductor Inc. v ZL50415 Table of Contents Data Sheet 13.1.1 Encapsulated View ........................................................................................................................71 13.1.2 Power and Ground Distribution ......................................................................................................72 13.2 Ball - Signal Descriptions .......................................................................................................................73 13.2.1 Ball Signal Descriptions .................................................................................................................73 13.3 Ball - Signal Name ..................................................................................................................................79 13.4 AC/DC Timing ........................................................................................................................................85 13.4.1 Absolute Maximum Ratings............................................................................................................85 13.4.2 DC Electrical Characteristics ..........................................................................................................85 13.4.3 Recommended Operation Conditions ............................................................................................86 13.5 Local Frame Buffer SBRAM Memory Interface........................................................................................87 13.5.1 Local SBRAM Memory Interface ....................................................................................................87 13.6 AC Characteristics ...................................................................................................................................88 13.6.1 Reduced Media Independent Interface ..........................................................................................88 13.6.2 LED Interface .................................................................................................................................89 13.6.3 SCANLINK SCANCOL Output Delay Timing ................................................................................89 13.6.4 MDIO Input Setup and Hold Timing ...............................................................................................90 13.6.5 I2C Input Setup Timing...................................................................................................................91 13.6.6 Serial Interface Setup Timing .........................................................................................................92 vi Zarlink Semiconductor Inc. Data Sheet List of Figures ZL50415 Figure 1 - ZL50415 System Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 2 - Data Transfer Format for I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 3 - ZL50415 SRAM Interface Block Diagram (DMAs for 10/1000 Ports Only) . . . . . . . . . . . . . . . . . . . . . . 17 Figure 4 - Priority Classification Rule. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 5 - Memory Configuration For: 1 bank, 1 Layer, 1MB total. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 6 - Memory Configuration For: 1 bank, 2 Layer, 2MB total. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 7 - Memory Configuration For: 1 bank, 1 Layer, 2MB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 8 - Buffer Partition Scheme Used to Implement Buffer Management in the ZL50415 . . . . . . . . . . . . . . . . 29 Figure 9 - GPSI (7WS) mode connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Figure 10 - SCAN LINK and SCAN COLLISON status diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Figure 11 - Timing Diagram of LED Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Figure 12 - Local Memory Interface - Input setup and hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Figure 13 - Local Memory Interface - Output valid delay timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Figure 14 - AC Characteristics - Reduced media independent Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Figure 15 - AC Characteristics - Reduced Media Independent Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Figure 16 - AC Characteristics - LED Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Figure 17 - SCANLINK SCANCOL Output Delay Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Figure 18 - SCANLINK, SCANCOL Setup Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Figure 19 - MDIO Input Setup and Hold Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Figure 20 - MDIO Output Delay Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Figure 21 - I2C Input Setup Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Figure 22 - I2C Output Delay Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Figure 23 - Serial Interface Setup Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Figure 24 - Serial Interface Output Delay Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Zarlink Semiconductor Inc. vii ZL50415 Data Sheet viii Zarlink Semiconductor Inc. Data Sheet List of Tables ZL50415 Table 1 - Memory Configuration ............................................................................................................................. 17 Table 2 - Memory Map ........................................................................................................................................... 17 Table 3 - Supported Memory Configurations (Pipeline SBRAM Mode) ................................................................. 21 Table 4 - Options for Memory Configuration .......................................................................................................... 21 Table 5 - Two-dimensional World Traffic................................................................................................................ 25 Table 6 - Four QoS Configurations for a 10/100 Mbps Port................................................................................... 26 Table 7 - WRED Drop Thresholds.......................................................................................................................... 27 Table 8 - Mapping between ZL50415 and IETF Diffserv Classes for 10/100 Ports ............................................... 30 Table 9 - ZL50415 Features Enabling IETF Diffserv Standards ............................................................................ 30 Table 10 - AC Characteristics - Local frame buffer SBRAM Memory Interface..................................................... 88 Table 11 - AC Characteristics - Reduced Media Independent Interface ............................................................... 88 Table 12 - AC Characteristics - LED Interface ...................................................................................................... 89 Table 13 - SCANLINK, SCANCOL Timing ............................................................................................................. 90 Table 14 - MDIO Timing ......................................................................................................................................... 90 Table 15 - I2C Timing............................................................................................................................................. 91 Table 16 - Serial Interface Timing .......................................................................................................................... 92 Zarlink Semiconductor Inc. ix ZL50415 Data Sheet x Zarlink Semiconductor Inc. Data Sheet 1.0 1.1 ZL50415 Block Functionality Frame Data Buffer (FDB) Interfaces The FDB interface supports SBRAM memory at 100 MHz. To ensure a non-blocking switch, one memory domain with a 64 bit wide memory bus is required. At 100 MHz, the aggregate memory bandwidth is 6.4 Gbps, which is enough to support 16 10/100 Mbps. The Switching Database is also located in the external SRAM; it is used for storing MAC addresses and their physical port number. 1.2 10/100 MAC Module (RMAC) The 10/100 Media Access Control module provides the necessary buffers and control interface between the Frame Engine (FE) and the external physical device (PHY). The ZL50415 has two interfaces, RMII or Serial (only for 10M). The 10/100 MAC of the ZL50415 device meets the IEEE 802.3 specification. It is able to operate in either Half or Full Duplex mode with a back pressure/flow control mechanism. In addition, it will automatically retransmit upon collision for up to 16 total transmissions. The PHY address for 16 10/100 MAC are from 08h to 17h. 1.3 Configuration Interface Module The ZL50415 supports a serial and an I2C interface, which provides an easy way to configure the system. Once configured, the resulting configuration can be stored in an I2C EEPROM. 1.4 Frame Engine The main function of the frame engine is to forward a frame to its proper destination port or ports. When a frame arrives, the frame engine parses the frame header (64 bytes) and formulates a switching request, sent to the search engine, to resolve the destination port. The arriving frame is moved to the FDB. After receiving a switch response from the search engine, the frame engine performs transmission scheduling based on the frame's priority. The frame engine forwards the frame to the MAC module when the frame is ready to be sent. 1.5 Search Engine The Search Engine resolves the frame's destination port or ports according to the destination MAC address (L2). It also performs MAC learning, priority assignment, and trunking functions. 1.6 LED Interface The LED interface provides a serial interface for carrying 16 port status signals. 1.7 Internal Memory Several internal tables are required and are described as follows: * Frame Control Block (FCB) - Each FCB entry contains the control information of the associated frame stored in the FDB, e.g. frame size, read/write pointer, transmission priority, etc. * MCT Link Table - The MCT Link Table stores the linked list of MCT entries that have collisions in the external MAC Table. The external MAC table is located in the FDB Memory. Note: the external MAC table is located in the external SSRAM Memory. Zarlink Semiconductor Inc. 13 ZL50415 2.0 2.1 Data Sheet System Configuration Configuration Mode The ZL50415 can be configured by EEPROM (24C02 or compatible) via an I2C interface at boot time, or via a synchronous serial interface during operation. 2.2 I2C Interface The I2C interface uses two bus lines, a serial data line (SDA) and a serial clock line (SCL). The SCL line carries the control signals that facilitate the transfer of information from EEPROM to the switch. Data transfer is 8-bit serial and bidirectional, at 50 Kbps. Data transfer is performed between master and slave IC using a request / acknowledgment style of protocol. The master IC generates the timing signals and terminates data transfer. Figure 2 depicts the data transfer format. START SLAVE ADDRESS R/W ACK DATA 1 (8 bits) ACK DATA 2 ACK DATA M ACK STOP Figure 2 - Data Transfer Format for I C Interface 2 2.2.1 Start Condition Generated by the master (in our case, the ZL50415). The bus is considered to be busy after the Start condition is generated. The Start condition occurs if while the SCL line is High, there is a High-to-Low transition of the SDA line. Other than in the Start condition (and Stop condition), the data on the SDA line must be stable during the High period of SCL. The High or Low state of SDA can only change when SCL is Low. In addition, when the I2C bus is free, both lines are High. 2.2.2 Address The first byte after the Start condition determines which slave the master will select. The slave in our case is the EEPROM. The first seven bits of the first data byte make up the slave address. 2.2.3 Data Direction The eighth bit in the first byte after the Start condition determines the direction (R/W) of the message. A master transmitter sets this bit to W; a master receiver sets this bit to R. 2.2.4 Acknowledgment Like all clock pulses, the acknowledgment-related clock pulse is generated by the master. However, the transmitter releases the SDA line (High) during the acknowledgment clock pulse. Furthermore, the receiver must pull down the SDA line during the acknowledge pulse so that it remains stable Low during the High period of this clock pulse. An acknowledgment pulse follows every byte transfer. If a slave receiver does not acknowledge after any byte, then the master generates a Stop condition and aborts the transfer. If a master receiver does not acknowledge after any byte, then the slave transmitter must release the SDA line to let the master generate the Stop condition. 2.2.5 Data After the first byte containing the address, all bytes that follow are data bytes. Each byte must be followed by an acknowledge bit. Data is transferred MSB first. 2.2.6 Stop Condition Generated by the master. The bus is considered to be free after the Stop condition is generated. The Stop condition occurs if while the SCL line is High, there is a Low-to-High transition of the SDA line. The I2C interface serves the function of configuring the ZL50415 at boot time. The master is the ZL50415, and the slave is the EEPROM memory. Zarlink Semiconductor Inc. 14 Data Sheet 2.3 Synchronous Serial Interface ZL50415 The synchronous serial interface serves the function of configuring the ZL50415 not at boot time but via a PC. The PC serves as master and the ZL50415 serves as slave. The protocol for the synchronous serial interface is nearly identical to the I2C protocol. The main difference is that there is no acknowledgment bit after each byte of data transferred. The unmanaged ZL50415 uses a synchronous serial interface to program the internal registers. To reduce the number of signals required, the register address, command and data are shifted in serially through the D0 pin. STROBE- pin is used as the shift clock. AUTOFD- pin is used as data return path. Each command consists of four parts. * * * * START pulse Register Address Read or Write command Data to be written or read back Any command can be aborted in the middle by sending a ABORT pulse to the ZL50415. A START command is detected when D0 is sampled high when STROBE- rise and D0 is sampled low when STROBE- fall. An ABORT command is detected when D0 is sampled low when STROBE- rise and D0 is sampled high when STROBE- fall. 2.3.1 Write Command STROBE2 Extra clocks after last transfer D0 A0 START A1 A2 ... A9 A10 A11 W D0 D1 D2 D3 D4 D5 D6 D7 DATA ADDRESS COMMAND 2.3.2 Read Command STROBE- D0 A0 START A1 A2 ... A9 A10 A11 R DATA ADDRESS COMMAND AUTOFD- D0 D1 D2 D3 D4 D5 D6 D7 All registers in ZL50415 can be modified through this synchronous serial interface. Zarlink Semiconductor Inc. 15 ZL50415 3.0 3.1 Data Sheet ZL50415 Data Forwarding Protocol Unicast Data Frame Forwarding When a frame arrives, it is assigned a handle in memory by the Frame Control Buffer Manager (FCB Manager). An FCB handle will always be available, because of advance buffer reservations. The memory (SRAM) interface is a 64-bit bus connected to SRAM bank. The Receive DMA (RxDMA) is responsible for multiplexing the data and the address. On a port's "turn," the RxDMA will move 8 bytes (or up to the end-of-frame) from the port's associated RxFIFO into memory (Frame Data Buffer, or FDB). Once an entire frame has been moved to the FDB, and a good end-of-frame (EOF) has been received, the Rx interface makes a switch request. The RxDMA arbitrates among multiple switch requests. The switch request consists of the first 64 bytes of a frame, containing among other things, the source and destination MAC addresses of the frame. The search engine places a switch response in the switch response queue of the frame engine when done. Among other information, the search engine will have resolved the destination port of the frame and will have determined that the frame is unicast. After processing the switch response, the Transmission Queue Manager (TxQ manager) of the frame engine is responsible for notifying the destination port that it has a frame to forward to it. But first, the TxQ manager has to decide whether or not to drop the frame, based on global FDB reservations and usage, as well as TxQ occupancy at the destination. If the frame is not dropped, then the TxQ manager links the frame's FCB to the correct per-port-per-class TxQ. Unicast TxQ's are linked lists of transmission jobs, represented by their associated frames' FCB's. There is one linked list for each transmission class for each port. There are 4 transmission classes for each of the 16 10/ 100 ports The TxQ manager is responsible for scheduling transmission among the queues representing different classes for a port. When the port control module determines that there is room in the MAC Transmission FIFO (TxFIFO) for another frame, it requests the handle of a new frame from the TxQ manager. The TxQ manager chooses among the head-of-line (HOL) frames from the per-class queues for that port, using a Zarlink Semiconductor scheduling algorithm. The Transmission DMA (TxDMA) is responsible for multiplexing the data and the address. On a port's turn, the TxDMA will move 8 bytes (or up to the EOF) from memory into the port's associated TxFIFO. After reading the EOF, the port control requests a FCB release for that frame. The TxDMA arbitrates among multiple buffer release requests. The frame is transmitted from the TxFIFO to the line. 3.2 Multicast Data Frame Forwarding After receiving the switch response, the TxQ manager has to make the dropping decision. A global decision to drop can be made, based on global FDB utilization and reservations. If so, then the FCB is released and the frame is dropped. In addition, a selective decision to drop can be made, based on the TxQ occupancy at some subset of the multicast packet's destinations. If so, then the frame is dropped at some destinations but not others, and the FCB is not released. If the frame is not dropped at a particular destination port, then the TxQ manager formats an entry in the multicast queue for that port and class. Multicast queues are physical queues (unlike the linked lists for unicast frames). There are 2 multicast queues for each of the 16 10/100 ports. The queue with higher priority has room for 32 entries and the queue with lower priority has room for 64 entries. There is one multicast queue for every two priority classes. For the 10/100 ports to map the 8 transmit priorities into 2 multicast queues, the 2 LSB are discarded. During scheduling, the TxQ manager treats the unicast queue and the multicast queue of the same class as one logical queue. The older head of line of the two queues is forwarded first. The port control requests a FCB release only after the EOF for the multicast frame has been read by all ports to which the frame is destined. 16 Zarlink Semiconductor Inc. Data Sheet 4.0 4.1 ZL50415 Memory Interface Overview The ZL50415 provides a 64-bit-wide SRAM bank with a 64-bit. Each DMA can read and write from the SRAM bank. The following figure provides an overview of the ZL50415 SRAM bank. SRAM TX DMA 0-7 TX DMA 8-15 RX DMA 0-7 RX DMA 8-15 Figure 3 - ZL50415 SRAM Interface Block Diagram (DMAs for 10/1000 Ports Only) 4.2 Detailed Memory Information Because the bus for each bank is 64 bits wide, frames are broken into 8-byte granules, written to and read from memory. 4.3 Memory Requirements To support 64K MAC address, 2 MB memory is required. When VLAN support is enabled, 512 entries of the MAC address table are used for storing the VLAN ID at VLAN Index Mapping Table. Up to 1K Ethernet frame buffers are supported and they will use 1.5 MB of memory. Each frame uses 1536 bytes. The maximum system memory requirement is 2 MB. If less memory is desired, the configuration can scale down. Memory Bank 1M 2M 1K 2K Frame Buffer Max MAC Address 32K 64K Table 1 - Memory Configuration 1M Bank 0.75M 0.25M 2M Bank 1.5M 0.5M Frame Data Buffer (FDR) Area MAC Address Control Table (MCT) Area Table 2 - Memory Map Zarlink Semiconductor Inc. 17 ZL50415 5.0 5.1 Data Sheet Search Engine Search Engine Overview The ZL50415 search engine is optimized for high throughput searching, with enhanced features to support: * * * * * * Up to 64K MAC addresses 2 groups of port trunking Traffic classification into 4 transmission priorities, and 2 drop precedence levels Flooding, Broadcast, Multicast Storm Control MAC address learning and aging Port based VLAN 5.2 Basic Flow Shortly after a frame enters the ZL50415 and is written to the Frame Data Buffer (FDB), the frame engine generates a Switch Request, which is sent to the search engine. The switch request consists of the first 64 bytes of the frame, which contain all the necessary information for the search engine to perform its task. When the search engine is done, it writes to the Switch Response Queue, and the frame engine uses the information provided in that queue for scheduling and forwarding. In performing its task, the search engine extracts and compresses the useful information from the 64-byte switch request. Among the information extracted are the source and destination MAC addresses, the transmission and discard priorities, whether the frame is unicast or multicast. Requests are sent to the external SRAM to locate the associated entries in the external hash table. When all the information has been collected from external SRAM, the search engine has to compare the MAC address on the current entry with the MAC address for which it is searching. If it is not a match, the process is repeated on the internal MCT Table. All MCT entries other than the first of each linked list are maintained internal to the chip. If the desired MAC address is still not found, then the result is either learning (source MAC address unknown) or flooding (destination MAC address unknown). In addition, port based VLAN information is used to select the correct set of destination ports for the frame (for multicast), or to verify that the frame's destination port is associated with the VLAN (for unicast). If the destination MAC address belongs to a port trunk, then the trunk number is retrieved instead of the port number. But on which port of the trunk will the frame be transmitted? This is easily computed using a hash of the source and destination MAC addresses. When all the information is compiled, the switch response is generated, as stated earlier. 5.3 5.3.1 Search, Learning, and Aging MAC Search The search block performs source MAC address and destination MAC address searching. As we indicated earlier, if a match is not found, then the next entry in the linked list must be examined, and so on until a match is found or the end of the list is reached. The port based VLAN bitmap is used to determine whether the frame should be forwarded to the outgoing port. When the egress port is not included in the ingress port VLAN bitmap, the packet is discarded. The MAC search block is also responsible for updating the source MAC address timestamp and the VLAN port association timestamp, used for aging. 5.3.2 Learning The learning module learns new MAC addresses and performs port change operations on the MCT database. The goal of learning is to update this database as the networking environment changes over time. Learning and port change will be performed based on memory slot availability only. 18 Zarlink Semiconductor Inc. Data Sheet 5.3.3 Aging ZL50415 Aging time is controlled by register 400h and 401h. The aging module scans and ages MCT entries based on a programmable "age out" time interval. As we indicated earlier, the search module updates the source MAC address timestamps for each frame it processes. When an entry is ready to be aged, the entry is removed from the table. 5.4 Quality of Service Quality of Service (QoS) refers to the ability of a network to provide better service to selected network traffic over various technologies. Primary goals of QoS include dedicated bandwidth, controlled jitter and latency (required by some real-time and interactive traffic), and improved loss characteristics. Traditional Ethernet networks have had no prioritization of traffic. Without a protocol to prioritize or differentiate traffic, a service level known as "best effort" attempts to get all the packets to their intended destinations with minimum delay; however, there are no guarantees. In a congested network or when a low-performance switch/router is overloaded, "best effort" becomes unsuitable for delay-sensitive traffic and mission-critical data transmission. The advent of QoS for packet-based systems accommodates the integration of delay-sensitive video and multimedia traffic onto any existing Ethernet network. It also alleviates the congestion issues that have previously plagued such "best effort" networking systems. QoS provides Ethernet networks with the breakthrough technology to prioritize traffic and ensure that a certain transmission will have a guaranteed minimum amount of bandwidth. Extensive core QoS mechanisms are built into the ZL50415 architecture to ensure policy enforcement and buffering of the ingress port, as well as weighted fair-queue(WFQ) scheduling at the egress port. In the ZL50415, QoS-based policies sort traffic into a small number of classes and mark the packets accordingly. The QoS identifier provides specific treatment to traffic in different classes, so that different quality of service is provided to each class. Frame and packet scheduling and discarding policies are determined by the class to which the frames and packets belong. For example, the overall service given to frames and packets in the premium class will be better than that given to the standard class; the premium class is expected to experience lower loss rate or delay. The ZL50415 supports the following QoS techniques: * * * In a port-based setup, any station connected to the same physical port of the switch will have the same transmit priority. In a tag-based setup, a 3-bit field in the VLAN tag provides the priority of the packet. This priority can be mapped to different queues in the switch to provide QoS. In a TOS/DS-based set up, TOS stands for "Type of Service" that may include "minimize delay," "maximize throughput," or "maximize reliability." Network nodes may select routing paths or forwarding behaviors that are suitably engineered to satisfy the service request. In a logical port-based set up, a logical port provides the application information of the packet. Certain applications are more sensitive to delays than others; using logical ports to classify packets can help speed up delay sensitive applications, such as VoIP. * Zarlink Semiconductor Inc. 19 ZL50415 5.5 Priority Classification Rule Data Sheet Figure 4 shows the ZL50415 priority classification rule. Yes Fix Port Priority ? No Use Default Port Settings No No TOS Precedence over VLAN? (FCR Register, Bit 7) No No VLAN Tag ? IP Frame ? Yes Use Default Port Settings IP Yes Yes Yes No Use TOS Use Logical Port Yes Use VLAN Priority Use Logical Port Figure 4 - Priority Classification Rule 5.6 Port Based VLAN An administrator can use the PVMAP Registers to configure the ZL50415 for port-based VLAN. For example, ports 1-3 might be assigned to the Marketing VLAN, ports 4-6 to the Engineering VLAN, and ports 7-9 to the Administrative VLAN. The ZL50415 determines the VLAN membership of each packet by noting the port on which it arrives. From there, the ZL50415 determines which outgoing port(s) is/are eligible to transmit each packet, or whether the packet should be discarded. Destination Port Numbers Bit Map Port Registers Register for Port #0 PVMAP00_0[7:0] to PVMAP00_1[7:0] Register for Port #1 PVMAP01_0[7:0] to PVMAP01_1[7:0] Register for Port #2 PVMAP02_0[7:0] to PVMAP02_1[7:0] ... Register for Port #15 PVMAP15_0[7:0] to PVMAP15_1[7:0] 0 0 0 0 15 0 0 0 ... 2 1 1 0 1 1 1 0 0 0 1 0 For example, in the above table a 1 denotes that an outgoing port is eligible to receive a packet from an incoming port. A 0 (zero) denotes that an outgoing port is not eligible to receive a packet from an incoming port. 20 Zarlink Semiconductor Inc. Data Sheet In this example: * * * Data packets received at port #0 are eligible to be sent to outgoing ports 1 and 2. Data packets received at port #1 are eligible to be sent to outgoing ports 0, and 2. Data packets received at port #2 are not eligible to be sent to ports 0 and 1. ZL50415 5.7 Memory Configurations The ZL50415 supports the following memory configurations. . It supports 1M and 2M configurations. Configuration 1M (Bootstrap pin TSTOUT7 = open) Two 128K x 32 SRAM/bank or One 128K x 64 SRAM/bank 2M (Bootstrap pin TSTOUT7 = pull down) Two 256K x 32 SRAM/bank Connections Single Layer (Bootstrap pin TSTOUT13 = open) Double Layer (Bootstrap pin TSTOUT13 = pull down) Connect 0E# and WE# NA Four 128K x 32 SRAM/bank or Two 128K x 64 SRAM/bank Connect 0E0# and WE0# Connect 0E1# and WE1# Table 3 - Supported Memory Configurations (Pipeline SBRAM Mode) Frame Data Buffer Only Bank A 1M (SRAM) ZL50415 ZL50416 ZL50417 ZL50418 X X 2M (SRAM) X X X X X X Bank A and Bank B 1M/bank (SRAM) 2M/bank (SRAM) Table 4 - Options for Memory Configuration Zarlink Semiconductor Inc. 21 ZL50415 Bank A (1M One Layer) Data LA_D[63:32] Data Sheet Data LA_D[31:0] SRAM Memory 128K 32 bits Memory 128K 32 bits Address LA_A[19:3] Bootstraps: TSTOUT7 = Open, TSTOUT13 = Open, TSTOUT4 = Open Figure 5 - Memory Configuration For: 1 bank, 1 Layer, 1MB total Bank A (2M Two Layers) Data LA_D[63:32] Data LA_D[31:0] SRAM Memory 128K 32 bits SRAM Memory 128K 32 bits SRAM Memory 128K 32 bits SRAM Memory 128K 32 bits Address LA_A[19:3] Bootstraps: TSTOUT7 = Pull Down, TSTOUT13 = Pull Down, TSTOUT4 = Open Figure 6 - Memory Configuration For: 1 bank, 2 Layer, 2MB total 22 Zarlink Semiconductor Inc. Data Sheet Bank A (2M One Layer) Data LA_D[63:32] ZL50415 Data LA_D[31:0] SRAM Memory 256K 32 bits Memory 256K 32 bits Address LA_A[20:3] Bootstraps: TSTOUT7 = Pull Down, TSTOUT13 = Open, TSTOUT4 = Open Figure 7 - Memory Configuration For: 1 bank, 1 Layer, 2MB 6.0 6.1 Frame Engine Data Forwarding Summary When a frame enters the device at the RxMAC, the RxDMA will move the data from the MAC RxFIFO to the FDB. Data is moved in 8-byte granules in conjunction with the scheme for the SRAM interface. A switch request is sent to the Search Engine. The Search Engine processes the switch request. A switch response is sent back to the Frame Engine and indicates whether the frame is unicast or multicast, and its destination port or ports. A Transmission Scheduling Request is sent in the form of a signal notifying the TxQ manager. Upon receiving a Transmission Scheduling Request, the device will format an entry in the appropriate Transmission Scheduling Queue (TxSch Q) or Queues. There are 4 TxSch Q for each 10/100, one for each priority. Creation of a queue entry either involves linking a new job to the appropriate linked list if unicast, or adding an entry to a physical queue if multicast. When the port is ready to accept the next frame, the TxQ manager will get the head-of-line (HOL) entry of one of the TxSch Qs, according to the transmission scheduling algorithm (so as to ensure per-class quality of service). The unicast linked list and the multicast queue for the same port-class pair are treated as one logical queue. The older HOL between the two queues goes first. For 10/100 ports multicast queue 0 is associated with unicast queue 0 and multicast queue 1 is associated with unicast queue 2. The TxDMA will pull frame data from the memory and forward it granule-by-granule to the MAC TxFIFO of the destination port. 6.2 Frame Engine Details This section briefly describes the functions of each of the modules of the ZL50415 frame engine. 6.2.1 FCB Manager The FCB manager allocates FCB handles to incoming frames, and releases FCB handles upon frame departure. The FCB manager is also responsible for enforcing buffer reservations and limits. The default values can be determined by referring to Chapter 8. In addition, the FCB manager is responsible for buffer aging, and for linking unicast forwarding jobs to their correct TxSch Q. The buffer aging can be enabled or disabled by the bootstrap pin and the aging time is defined in register FCBAT. Zarlink Semiconductor Inc. 23 ZL50415 6.2.2 Rx Interface Data Sheet The Rx interface is mainly responsible for communicating with the RxMAC. It keeps track of the start and end of frame and frame status (good or bad). Upon receiving an end of frame that is good, the Rx interface makes a switch request. 6.2.3 RxDMA The RxDMA arbitrates among switch requests from each Rx interface. It also buffers the first 64 bytes of each frame for use by the search engine when the switch request has been made. 6.2.4 TxQ Manager First, the TxQ manager checks the per-class queue status and global reserved resource situation, and using this information, makes the frame dropping decision after receiving a switch response. If the decision is not to drop, the TxQ manager requests that the FCB manager link the unicast frame's FCB to the correct per-port-perclass TxQ. If multicast, the TxQ manager writes to the multicast queue for that port and class. The TxQ manager can also trigger source port flow control for the incoming frame's source if that port is flow control enabled. Second, the TxQ manager handles transmission scheduling; it schedules transmission among the queues representing different classes for a port. Once a frame has been scheduled, the TxQ manager reads the FCB information and writes to the correct port control module. 6.3 Port Control The port control module calculates the SRAM read address for the frame currently being transmitted. It also writes start of frame information and an end of frame flag to the MAC TxFIFO. When transmission is done, the port control module requests that the buffer be released. 6.4 TxDMA The TxDMA multiplexes data and address from port control, and arbitrates among buffer release requests from the port control modules. 7.0 7.1 Quality of Service and Flow Control Model Quality of service is an all-encompassing term for which different people have different interpretations. In general, the approach to quality of service described here assumes that we do not know the offered traffic pattern. We also assume that the incoming traffic is not policed or shaped. Furthermore, we assume that the network manager knows his applications, such as voice, file transfer, or web browsing, and their relative importance. The manager can then subdivide the applications into classes and set up a service contract with each. The contract may consist of bandwidth or latency assurances per class. Sometimes it may even reflect an estimate of the traffic mix offered to the switch. As an added bonus, although we do not assume anything about the arrival pattern, if the incoming traffic is policed or shaped, we may be able to provide additional assurances about our switch's performance. 24 Zarlink Semiconductor Inc. Data Sheet ZL50415 Table 6 shows examples of QoS applications with three transmission priorities, but best effort (P0) traffic may form a fourth class with no bandwidth or latency assurances. Goals Total Assured Bandwidth (user defined) Low Drop Probability (low-drop) Apps: phone calls, circuit emulation. Latency: < 1 ms. Drop: No drop if P3 not oversubscribed. Apps: interactive apps, Web business. Latency: < 4-5 ms. Drop: No drop if P2 not oversubscribed. Apps: emails, file backups. Latency: < 16 ms desired, but not critical. Drop: No drop if P1 not oversubscribed. High Drop Probability (high-drop) Apps: training video. Latency: < 1 ms. Drop: No drop if P3 not oversubscribed; first P3 to drop otherwise. Apps: non-critical interactive apps. Latency: < 4-5 ms. Drop: No drop if P2 not oversubscribed; firstP2 to drop otherwise. Apps: casual web browsing. Latency: < 16 ms desired, but not critical. Drop: No drop if P1 not oversubscribed; first to drop otherwise. Highest transmission priority, P3 50 Mbps Middle transmission priority, P2 37.5 Mbps Low transmission priority, P1 12.5 Mbps Total 100 Mbps Table 5 - Two-dimensional World Traffic A class is capable of offering traffic that exceeds the contracted bandwidth. A well-behaved class offers traffic at a rate no greater than the agreed-upon rate. By contrast, a misbehaving class offers traffic that exceeds the agreed-upon rate. A misbehaving class is formed from an aggregation of misbehaving microflows. To achieve high link utilization, a misbehaving class is allowed to use any idle bandwidth. However, such leniency must not degrade the quality of service (QoS) received by well-behaved classes. As Table 6 illustrates, the six traffic types may each have their own distinct properties and applications. As shown, classes may receive bandwidth assurances or latency bounds. In the table, P3, the highest transmission class, requires that all frames be transmitted within 1 ms, and receives 50% of the 100 Mbps of bandwidth at that port. Best-effort (P0) traffic forms a fourth class that only receives bandwidth when none of the other classes have any traffic to offer. It is also possible to add a fourth class that has strict priority over the other three; if this class has even one frame to transmit, then it goes first. In the ZL50415, each 10/100 Mbps port will support four total classes, and each 1000 Mbps port will support eight classes. We will discuss the various modes of scheduling these classes in the next section. In addition, each transmission class has two subclasses, high-drop and low-drop. Well-behaved users should rarely lose packets. But poorly behaved users - users who send frames at too high a rate - will encounter frame loss, and the first to be discarded will be high-drop. Of course, if this is insufficient to resolve the congestion, eventually some low-drop frames are dropped, and then all frames in the worst case. Table 6 shows that different types of applications may be placed in different boxes in the traffic table. For example, casual web browsing fits into the category of high-loss, high-latency-tolerant traffic, whereas VoIP fits into the category of low-loss, low-latency traffic. Zarlink Semiconductor Inc. 25 ZL50415 7.2 Four QoS Configurations Data Sheet There are four basic pieces to QoS scheduling in the ZL50415: strict priority (SP), delay bound, weighted fair queuing (WFQ), and best effort (BE). Using these four pieces, there are four different modes of operation, as shown in Table 5 and Table 6. For 10/100 Mbps ports, these modes are selected by the following registers: QOSC24 [7:6] QOSC28 [7:6] QOSC32 [7:6] QOSC36 [7:6] CREDIT_C00 CREDIT_C10 CREDIT_C20 CREDIT_C30 P3 Op1 (default) Op2 Op3 Op4 Delay Bound SP SP WFQ P2 P1 P0 BE Delay Bound WFQ BE Table 6 - Four QoS Configurations for a 10/100 Mbps Port The default configuration for a 10/100 Mbps port is three delay-bounded queues and one best-effort queue. The delay bounds per class are 0.8 ms for P3, 2 ms for P2, and 12.8 ms for P1. Best effort traffic is only served when there is no delay-bounded traffic to be served. We have a second configuration for a 10/100 Mbps port in which there is one strict priority queue, two delay bounded queues, and one best effort queue. The delay bounds per class are 3.2 ms for P2 and 12.8 ms for P1. If the user is to choose this configuration, it is important that P3 (SP) traffic be either policed or implicitly bounded (e.g. if the incoming P3 traffic is very light and predictably patterned). Strict priority traffic, if not admission-controlled at a prior stage to the ZL50415, can have a deleterious effect on all other classes' performance. The third configuration for a 10/100 Mbps port contains one strict priority queue and three queues receiving a bandwidth partition via WFQ. As in the second configuration, strict priority traffic needs to be carefully controlled. In the fourth configuration, all queues are served using a WFQ service discipline. 7.3 Delay Bound In the absence of a sophisticated QoS server and signaling protocol, the ZL50415 may not know the mix of incoming traffic ahead of time. To cope with this uncertainty, our delay assurance algorithm dynamically adjusts its scheduling and dropping criteria, guided by the queue occupancies and the due dates of their head-of-line (HOL) frames. As a result, we assure latency bounds for all admitted frames with high confidence, even in the presence of system-wide congestion. Our algorithm identifies misbehaving classes and intelligently discards frames at no detriment to well-behaved classes. Our algorithm also differentiates between high-drop and lowdrop traffic with a weighted random early drop (WRED) approach. Random early dropping prevents congestion by randomly dropping a percentage of high-drop frames even before the chip's buffers are completely full, while still largely sparing low-drop frames. This allows high-drop frames to be discarded early, as a sacrifice for future low-drop frames. Finally, the delay bound algorithm also achieves bandwidth partitioning among classes. 7.4 Strict Priority and Best Effort When strict priority is part of the scheduling algorithm, if a queue has even one frame to transmit, it goes first. Two of our four QoS configurations include strict priority queues. The goal is for strict priority classes to be used for IETF expedited forwarding (EF), where performance guarantees are required. As we have indicated, it is 26 Zarlink Semiconductor Inc. Data Sheet ZL50415 important that strict priority traffic be either policed or implicitly bounded, so as to keep from harming other traffic classes. When best effort is part of the scheduling algorithm, a queue only receives bandwidth when none of the other classes have any traffic to offer. Two of our four QoS configurations include best effort queues. The goal is for best effort classes to be used for non-essential traffic, because we provide no assurances about best effort performance. However, in a typical network setting, much best effort traffic will indeed be transmitted, and with an adequate degree of expediency. Because we do not provide any delay assurances for best effort traffic, we do not enforce latency by dropping best effort traffic. Furthermore, because we assume that strict priority traffic is carefully controlled before entering the ZL50415, we do not enforce a fair bandwidth partition by dropping strict priority traffic. To summarize, dropping to enforce bandwidth or delay does not apply to strict priority or best effort queues. We only drop frames from best effort and strict priority queues when global buffer resources become scarce. 7.5 Weighted Fair Queuing In some environments - for example, in an environment in which delay assurances are not required, but precise bandwidth partitioning on small time scales is essential, WFQ may be preferable to a delay-bounded scheduling discipline. The ZL50415 provides the user with a WFQ option with the understanding that delay assurances can not be provided if the incoming traffic pattern is uncontrolled. The user sets four WFQ "weights" such that all weights are whole numbers and sum to 64. This provides per-class bandwidth partitioning with error within 2%. In WFQ mode, though we do not assure frame latency, the ZL50415 still retains a set of dropping rules that helps to prevent congestion and trigger higher level protocol end-to-end flow control. As before, when strict priority is combined with WFQ, we do not have special dropping rules for the strict priority queues, because the input traffic pattern is assumed to be carefully controlled at a prior stage. However, we do indeed drop frames from SP queues for global buffer management purposes. In addition, queue P0 for a 10/100 port are treated as best effort from a dropping perspective, though they still are assured a percentage of bandwidth from a WFQ scheduling perspective. What this means is that these particular queues are only affected by dropping when the global buffer count becomes low. 7.6 WRED Drop Threshold Management Support To avoid congestion, the Weighted Random Early Detection (WRED) logic drops packets according to specified parameters. The following table summarizes the behavior of the WRED logic. In KB (kilobytes) Level 1 N 120 Level 2 N 140 Level 3 N 160 Table 7 - WRED Drop Thresholds Px is the total byte count, in the priority queue x. The WRED logic has three drop levels, depending on the value of N, which is based on the number of bytes in the priority queues. If delay bound scheduling is used, N equals P3*16+P2*4+P1. If using WFQ scheduling, N equals P3+P2+P1. Each drop level from one to three has defined high-drop and low-drop percentages, which indicate the minimum and maximum percentages of the data that can be discarded. The X, Y Z percent can be programmed by the register RDRC0, RDRC1. In Level 3, all packets are dropped if the bytes in each priority queue exceed the threshold. Parameters A, B, C are the byte count thresholds for each priority queue. They can be programmed by the QOS control register (refer to the register group 5.) See Programming Qos Registers application note for more information. P3 P2 P1 High Drop X% P3 AKB P2 BKB P1 CKB Y% 100% Low Drop 0% Z% 100% Zarlink Semiconductor Inc. 27 ZL50415 7.7 Buffer Management Data Sheet Because the number of FDB slots is a scarce resource, and because we want to ensure that one misbehaving source port or class cannot harm the performance of a well-behaved source port or class, we introduce the concept of buffer management into the ZL50415. Our buffer management scheme is designed to divide the total buffer space into numerous reserved regions and one shared pool, as shown in Figure 8 on page 29. As shown in the figure, the FDB pool is divided into several parts. A reserved region for temporary frames stores frames prior to receiving a switch response. Such a temporary region is necessary, because when the frame first enters the ZL50415, its destination port and class are as yet unknown, and so the decision to drop or not needs to be temporarily postponed. This ensures that every frame can be received first before subjecting them to the frame drop discipline after classifying. Six reserved sections, one for each of the first six priority classes, ensure a programmable number of FDB slots per class. The lowest two classes do not receive any buffer reservation. Furthermore, even for 10/100 Mbps ports, a frame is stored in the region of the FDB corresponding to its class. As we have indicated, the eight classes use only four transmission scheduling queues for 10/100 Mbps ports, but as far as buffer usage is concerned, there are still eight distinguishable classes. Another segment of the FDB reserves space for each of the 24 regions. One parameters can be set for the source port reservation for 10/100 Mbps. These 16 reserved regions make sure that no well-behaved source port can be blocked by another misbehaving source port. In addition, there is a shared pool, which can store any type of frame. The frame engine allocates the frames first in the six priority sections. When the priority section is full or the packet has priority 1 or 0, the frame is allocated in the shared poll. Once the shared poll is full the frames are allocated in the section reserved for the source port. The following registers define the size of each section of the frame data buffer: PR100- Port Reservation for 10/100 Ports SFCB- Share FCB Size C2RS- Class 2 Reserve Size C3RS- Class 3 Reserve Size C4RS- Class 4 Reserve Size C5RS- Class 5 Reserve Size C6RS- Class 6 Reserve Size C7RS- Class 7 Reserve Size 28 Zarlink Semiconductor Inc. Data Sheet ZL50415 temporary reservation shared pool per-class reservation per-source reservations (24 10/100M, CPU) Figure 8 - Buffer Partition Scheme Used to Implement Buffer Management in the ZL50415 7.7.1 Dropping When Buffers Are Scarce Summarizing the two examples of local dropping discussed earlier in this chapter: * If a queue is a delay-bounded queue, we have a multilevel WRED drop scheme, designed to control delay and partition bandwidth in case of congestion. * If a queue is a WFQ-scheduled queue, we have a multilevel WRED drop scheme, designed to prevent congestion. In addition to these reasons for dropping, we also drop frames when global buffer space becomes scarce. The function of buffer management is to make sure that such dropping causes as little blocking as possible. 7.8 ZL50415 Flow Control Basics Because frame loss is unacceptable for some applications, the ZL50415 provides a flow control option. When flow control is enabled, scarcity of buffer space in the switch may trigger a flow control signal; this signal tells a source port that is sending a packet to this switch, to temporarily hold off. While flow control offers the clear benefit of no packet loss, it also introduces a problem for quality of service. When a source port receives an Ethernet flow control signal, all microflows originating at that port, wellbehaved or not, are halted. A single packet destined for a congested output can block other packets destined for uncongested outputs. The resulting head-of-line blocking phenomenon means that quality of service cannot be assured with high confidence when flow control is enabled. In the ZL50415, each source port can independently have flow control enabled or disabled. For flow control enabled ports, by default all frames are treated as lowest priority during transmission scheduling. This is done so that those frames are not exposed to the WRED Dropping scheme. Frames from flow control enabled ports feed to only one queue at the destination, the queue of lowest priority. What this means is that if flow control is enabled for a given source port, then we can guarantee that no packets originating from that port will be lost, but at the possible expense of minimum bandwidth or maximum delay assurances. In addition, these "downgraded" frames may only use the shared pool or the per-source reserved pool in the FDB; frames from flow control enabled sources may not use reserved FDB slots for the highest six classes (P2-P7). Zarlink Semiconductor Inc. 29 ZL50415 Data Sheet The ZL50415 does provide a system-wide option of permitting normal QoS scheduling (and buffer use) for frames originating from flow control enabled ports. When this programmable option is active, it is possible that some packets may be dropped, even though flow control is on. The reason is that intelligent packet dropping is a major component of the ZL50415's approach to ensuring bounded delay and minimum bandwidth for high priority flows. 7.8.1 Unicast Flow Control For unicast frames, flow control is triggered by source port resource availability. Recall that the ZL50415's buffer management scheme allocates a reserved number of FDB slots for each source port. If a programmed number of a source port's reserved FDB slots have been used, then flow control Xoff is triggered. Xon is triggered when a port is currently being flow controlled, and all of that port's reserved FDB slots have been released. Note that the ZL50415's per-source-port FDB reservations assure that a source port that sends a single frame to a congested destination will not be flow controlled. 7.8.2 Multicast Flow Control In unmanaged mode, flow control for multicast frames is triggered by a global buffer counter. When the system exceeds a programmable threshold of multicast packets, Xoff is triggered. Xon is triggered when the system returns below this threshold. In addition, each source port has a 15-bit port map recording which port or ports of the multicast frame's fanout were congested at the time Xoff was triggered. All ports are continuously monitored for congestion, and a port is identified as uncongested when its queue occupancy falls below a fixed threshold. When all those ports that were originally marked as congested in the port map have become uncongested, then Xon is triggered, and the 15-bit vector is reset to zero. 7.9 Mapping to IETF Diffserv Classes For 10/100 Mbps ports, the classes of Table 8 are merged in pairs--one class corresponding to NM+EF, two AF classes, and a single BE class. ZL IETF P3 NM+EF P2 AF0 P1 AF1 P0 BE0 Table 8 - Mapping between ZL50415 and IETF Diffserv Classes for 10/100 Ports Features of the ZL50415 that correspond to the requirements of their associated IETF classes are summarized in the table below. Network management (NM) and Expedited forwarding (EF) Assured forwarding (AF) * * * * * * * Best effort (BE) * * * Global buffer reservation for NM and EF Option of strict priority scheduling No dropping if admission controlled Programmable bandwidth partition, with option of WFQ service Option of delay-bounded service keeps delay under fixed levels even if not admission-controlled Random early discard, with programmable levels Global buffer reservation for each AF class Service only when other queues are idle means that QoS not adversely affected Random early discard, with programmable levels Traffic from flow control enabled ports automatically classified as BE Table 9 - ZL50415 Features Enabling IETF Diffserv Standards 30 Zarlink Semiconductor Inc. Data Sheet 8.0 8.1 * * ZL50415 Port Trunking Features and Restrictions * A port group (i.e. trunk) can include up to 4 physical ports, but all of the ports in a group must be in the same ZL50415. Load distribution among the ports in a trunk for unicast is performed using hashing based on source MAC address and destination MAC address. Three other options include source MAC address only, destination MAC address only, and source port (in bidirectional ring mode only). Load distribution for multicast is performed similarly. The ZL50415 also provides a safe fail-over mode for port trunking automatically. If one of the ports in the trunking group goes down, the ZL50415 will automatically redistribute the traffic over to the remaining ports in the trunk 8.2 Unicast Packet Forwarding The search engine finds the destination MCT entry, and if the status field says that the destination port found belongs to a trunk, then the group number is retrieved instead of the port number. In addition, if the source address belongs to a trunk, then the source port's trunk membership register is checked. A hash key, based on some combination of the source and destination MAC addresses for the current packet, selects the appropriate forwarding port. 8.3 Multicast Packet Forwarding For multicast packet forwarding, the device must determine the proper set of ports from which to transmit the packet based on the VLAN index and hash key. Two functions are required in order to distribute multicast packets to the appropriate destination ports in a port trunking environment. Determining one forwarding port per group. For multicast packets, all but one port per group, the forwarding port, must be excluded. Preventing the multicast packet from looping back to the source trunk. The search engine needs to prevent a multicast packet from sending to a port that is in the same trunk group with the source port. This is because, when we select the primary forwarding port for each group, we do not take the source port into account. To prevent this, we simply apply one additional filter, so as to block that forwarding port for this multicast packet. 8.4 Trunking 2 trunk groups are supported. Groups 0 and 1 can trunk up to 4 10/100 ports. The supported combinations are shown in the following table. Group 0 Port 0 Port 1 ! ! ! ! ! ! Port 2 Port 3 ! ! ! Zarlink Semiconductor Inc. 31 ZL50415 Select via trunk0_mode register Group 1 Port 4 ! ! Port 5 ! ! ! ! Port 6 Port 7 Data Sheet Select via trunk1_mode register The trunks are individually enabled/disabled by controlling pin trunk 0,1. 9.0 9.1 Port Mirroring Port Mirroring Features The received or transmitted data of any 10/100 port in the ZL50415 chip can be "mirrored" to any other port. We support two such mirrored source-destination pairs. A mirror port cannot also serve as a data port. 9.2 * Setting Registers for Port Mirroring MIRROR1_SRC: Sets the source port for the first port mirroring pair. Bits [4:0] select the source port to be mirrored. An illegal port number is used to disable mirroring (which is the default setting). Bit [5] is used to select between ingress (Rx) or egress (Tx) data. MIRROR1_DEST: Sets the destination port for the first port mirroring pair. Bits [4:0] select the destination port to be mirrored. MIRROR2_SRC: Sets the source port for the second port mirroring pair. Bits [4:0] select the source port to be mirrored. An illegal port number is used to disable mirroring (which is the default setting). Bit [5] is used to select between ingress (Rx) or egress (Tx) data. MIRROR2_DEST: Sets the destination port for the second port mirroring pair. Bits [4:0] select the destination port to be mirrored. The default is port 0. * * * Refer to Port Mirroring Application Notes for further information. 10.0 10.1 GPSI (7WS) Interface GPSI connection The 10/100 RMII ethernet port can function in GPSI (7WS) mode when the corresponding TXEN pin is strapped low with a 1K pull down resistor. In this mode, the TXD[0], TXD[1], RXD[0] and RXD[1] serve as TX data, TX clock, RX data and RX clock respectively. The link status and collision from the PHY are multiplexed and shifted into the switch device through external glue logic. The duplex of the port can be controlled by programming the ECR register. The GPSI interface can be operated in port based VLAN mode only. 32 Zarlink Semiconductor Inc. Data Sheet crs rxd rx_clk tx_clk txd txen Port 0 Ethernet PHY link0 col0 ZL50415 CRS_DV RXD[0] RXD[1] TXD[1] TXD[0] TXEN link1 260X col1 link2 col2 link15 col15 Port 15 Ethernet PHY SCAN_LINK SCAN_COL SCAN_CLK Link Serializer (CPLD) Collision Serializer (CPLD) Figure 9 - GPSI (7WS) mode connection diagram 10.2 SCAN LINK and SCAN COL interface An external CPLD logic is required to take the link signals and collision signals from the GPSI PHYS and shift them into the switch device. The switch device will drive out a signature to indicate the start of the sequence. After that, the CPLD should shift in the link and collision status of the PHYS as shown in the figure. The extra link status indicates the polarity of the link signal. One indicates the polarity of the link signal is active high. Zarlink Semiconductor Inc. 33 ZL50415 Data Sheet scan_clk scan_link/ scan_col 25 cycles for link/ 24 cycles for col Driven by ZL5041x Drived by VTX260x Driven by CPLD Drived by CPLD Total 32 cycles period Figure 10 - SCAN LINK and SCAN COLLISON status diagram 11.0 11.1 LED Interface LED Interface Introduction A serial output channel provides port status information from the ZL50415 chips. It requires three additional pins. * * * LED_CLK at 12.5 MHz LED_SYN a sync pulse that defines the boundary between status frames LED_DATA a continuous serial stream of data for all status LEDs that repeats once every frame time A low cost external device (44 pin PAL) is used to decode the serial data and to drive an LED array for display. This device can be customized for different needs. 11.2 Port Status In the ZL50415, each port has 8 status indicators, each represented by a single bit. The 8 LED status indicators are: * * * * * * * * Bit 0: Flow control Bit 1:Transmit data Bit 2: Receive data Bit 3: Activity (where activity includes either transmission or reception of data) Bit 4: Link up Bit 5: Speed (1= 100 Mb/s; 0= 10 Mb/s) Bit 6: Full-duplex Bit 7: Collision Eight clocks are required to cycle through the eight status bits for each port. When the LED_SYN pulse is asserted, the LED interface will present 256 LED clock cycles with the clock cycles providing information for the following ports. Port 0 (10/100): cycles #0 to cycle #7 Port 1 (10/100): cycles#8 to cycle #15 Port 2 (10/100): cycle #16 to cycle #23 ... Port 14 (10/100): cycle #112 to cycle #119 34 Zarlink Semiconductor Inc. Data Sheet Port 15 (10/100): cycle #120 to cycle #127 Reserved: cycle #128 to cycle #207 Byte 26 (additional status): cycle #208 to cycle #215 Byte 27 (additional status): cycle #216 to cycle #223 Cycles #224 to 256 present data with a value of zero. Byte 26 and byte 27 provides bist status * * * * * * * * * 26[1:0] : Reserved 26[2]: initialization done 26[3]: initialization start 26[4]: checksum ok 26[5]: link_init_complete 26[6]: bist_fail 26[7]: ram_error 27[0]: bist_in_process 27[1]: bist_done ZL50415 11.3 LED Interface Timing Diagram The signal from the ZL50415 to the LED decoder is shown in Figure 11. Figure 11 - Timing Diagram of LED Interface Zarlink Semiconductor Inc. 35 ZL50415 12.0 12.1 Data Sheet Register Definition ZL50415 Register Description Register Description CPU Addr (Hex) R/W I2C Addr (Hex) Default Notes 0. ETHERNET Port Control Registers Substitute [N] with Port number (0..F) ECR1P"N" ECR2P"N" Port Control Register 1 for Port N Port Control Register 2 for Port N 000 + 2 x N 001 + 2 x N R/W R/W 000-018 01B-033 020 000 1. VLAN Control Registers Substitute [N] with Port number (0..F) AVTCL AVTCH PVMAP"N"_0 PVMAP"N"_1 PVMAP"N"_3 PVMODE VLAN Type Code Register Low VLAN Type Code Register High Port "N" Configuration Register 0 Port "N" Configuration Register 1 Port "N" Configuration Register 3 VLAN Operating Mode 100 101 102 + 4N 103 + 4N 105 + 4N 170 R/W R/W R/W R/W R/W R/W 036 037 038-050 053-06B 089-0A1 0A4 000 081 0FF 0FF 007 000 2. TRUNK Control Registers TRUNK0_ MODE TRUNK1_ MODE Trunk Group 0 Mode Trunk Group 1 Mode 203 20B R/W R/W 0A5 0A6 003 003 3. CPU Port Configuration TX_AGE Transmission Queue Aging Time 325 R/W 0A7 008 4. Search Engine Configurations AGETIME_LOW MAC Address Aging Time Low 400 R/W 0A8 2M:05C / 4M:02E 000 000 AGETIME_ HIGH SE_OPMODE MAC Address Aging Time High Search Engine Operating Mode 401 403 R/W R/W 0A9 NA 5. Buffer Control and QOS Control FCBAT QOSC FCR AVPML AVPMM AVPMH TOSPML TOSPMM TOSPMH FCB Aging Timer QOS Control Flooding Control Register VLAN Priority Map Low VLAN Priority Map Middle VLAN Priority Map High TOS Priority Map Low TOS Priority Map Middle TOS Priority Map High 500 501 502 503 504 505 506 507 508 R/W R/W R/W R/W R/W R/W R/W R/W R/W 0AA 0AB 0AC 0AD 0AE 0AF 0B0 0B1 0B2 0FF 000 008 000 000 000 000 000 000 36 Zarlink Semiconductor Inc. Data Sheet Register AVDM TOSDML BMRC UCC Description VLAN Discard Map TOS Discard Map Broadcast/Multicast Rate Control Unicast Congestion Control CPU Addr (Hex) 509 50A 50B 50C R/W R/W R/W R/W R/W I2C Addr (Hex) 0B3 0B4 0B5 0B6 ZL50415 Default 000 000 000 1M:008 / 2M:010 050 1M:035 / 2M:058 1M:046 / 2M:0E6 000 000 000 000 000 000 000 000 000 000 000 08F 088 000 000 000 000 000 Notes MCC PR100 Multicast Congestion Control Port Reservation for 10/100 Ports 50D 50E R/W R/W 0B7 0B8 SFCB Share FCB Size 510 R/W 0BA C2RS C3RS C4RS C5RS C6RS C7RS QOSC"N" Class 2 Reserve Size Class 3 Reserve Size Class 4 Reserve Size Class 5 Reserve Size Class 6 Reserve Size Class 7 Reserve Size QOS Control (N=0 - 5) QOS Control (N=6 - 11) QOS Control (N=12 - 23) QOS Control (N=24 - 59) 511 512 513 514 515 516 517- 51C 51D- 522 523- 52E 52F- 552 517 512 553 554 580 + 2N 581 + 2N 590 591 592 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0BB 0BC 0BD 0BE 0BF 0C0 0C1-0C6 NA 0C7-0D2 NA 0C1-0D2 0FB 0FC 0D60DD 0DE0E5 0E6 0E7 0E8 QOSC"N" RDRC0 RDRC1 USER_ PORT"N"_LOW USER_ PORT"N"_HIGH USER_ PORT1:0_ PRIORITY USER_ PORT3:2_ PRIORITY USER_ PORT5:4_ PRIORITY QOS Control (N=0 59) WRED Drop Rate Control 0 WRED Drop Rate Control 1 User Define Logical Port "N" Low (N=0-7) User Define Logical Port "N" High User Define Logic Port 1 and 0 Priority User Define Logic Port 3 and 2 Priority User Define Logic Port 5 and 4 Priority Zarlink Semiconductor Inc. 37 ZL50415 Register USER_ PORT7:6_PRI ORITY USER_PORT_ ENABLE WLPP10 WLPP32 WLPP54 WLPP76 WLPE RLOWL RLOWH RHIGHL RHIGHH RPRIORITY Description User Define Logic Port 7 and 6 Priority User Define Logic Port Enable Well known Logic Port Priority for 1 and 0 Well known Logic Port Priority for 3 and 2 Well known Logic Port Priority for 5 and 4 Well-known Logic Port Priority for 7&6 Well known Logic Port Enable User Define Range Low Bit7:0 User Define Range Low Bit 15:8 User Define Range High Bit 7:0 User Define Range High Bit 15:8 User Define Range Priority CPU Addr (Hex) 593 R/W R/W I2C Addr (Hex) 0E9 Data Sheet Default 000 Notes 594 595 596 597 598 599 59A 59B 59C 59D 59E R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0EA 0EB 0EC 0ED 0EE 0EF 0F4 0F5 0D3 0D4 0D5 000 000 000 000 000 000 000 000 000 000 000 6. MISC Configuration Registers MII_OP0 MII_OP1 FEN MIIC0 MIIC1 MIIC2 MIIC3 MIID0 MIID1 LED SUM MII Register Option 0 MII Register Option 1 Feature Registers MII Command Register 0 MII Command Register 1 MII Command Register 2 MII Command Register 3 MII Data Register 0 MII Data Register 1 LED Control Register EEPROM Checksum Register 600 601 602 603 604 605 606 607 608 609 60B R/W R/W R/W R/W R/W R/W R/W RO RO R/W R/W 0F0 0F1 0F2 N/A N/A N/A N/A N/A N/A 0F3 0FF 000 000 010 000 000 000 000 N/A N/A 000 000 7. Port Mirroring Controls MIRROR1_SRC MIRROR1_ DEST MIRROR2_SRC Port Mirror 1 Source Port Port Mirror 1 Destination Port Port Mirror 2 Source Port 700 701 702 R/W R/W R/W N/A N/A N/A 07F 017 0FF 38 Zarlink Semiconductor Inc. Data Sheet Register MIRROR2_ DEST Description Port Mirror 2 Destination Port CPU Addr (Hex) 703 R/W R/W I2C Addr (Hex) N/A ZL50415 Default 000 Notes F. Device Configuration Register GCR DCR DCR1 DPST DTST DA Global Control Register Device Status and Signature Register Chip status Device Port Status Register Data read back register DA Register F00 F01 F02 F03 F04 FFF R/W RO RO R/W RO RO N/A N/A N/A N/A N/A N/A 000 N/A N/A 000 N/A DA 12.2 12.2.1 * * Group 0 Address MAC Ports Group ECR1Pn: Port N Control Register I2C Address 000-018; CPU Address:0000+2xN (N = port number) Accessed by serial interface and I2C (R/W) 7 6 5 A-FC 4 3 2 1 0 Sp State Port Mode Bit [0] * * * * * 1 - Flow Control Off 0 - Flow Control On When Flow Control On: In half duplex mode, the MAC transmitter applies back pressure for flow control. In full duplex mode, the MAC transmitter sends Flow Control frames when necessary. The MAC receiver interprets and processes incoming flow control frames. The Flow Control Frame Received counter is incremented whenever a flow control is received. When Flow Control off: In half duplex mode, the MAC Transmitter does not assert flow control by sending flow control frames or jamming collision. In full duplex mode, the Mac transmitter does not send flow control frames. The MAC receiver does not interpret or process the flow control frames. The Flow Control Frame Received counter is not incremented. 1 - Half Duplex - Only 10/100 mode 0 - Full Duplex 1 - 10Mbps 0 - 100Mbps * * * Bit [1] Bit [2] * * * * Zarlink Semiconductor Inc. 39 ZL50415 Bit [4:3] * * * * Bit [5] * * * * Data Sheet 00 - Automatic Enable Auto Neg. This enables hardware state machine for auto-negotiation. 01 - Limited Disable auto Neg. This disables hardware for speed autonegotiation. Poll MII for link status. 10 - Link Down. Disable auto Neg. state machine and force link down (disable the port) 11 - Link Up. User ERC1 [2:0] for config. Asymmetric Flow Control Enable 0 - Disable asymmetric flow control 1 - Enable asymmetric flow control Asymmetric Flow Control Enable. When this bit is set and flow control is on (bit[0] = 0, don't send out a flow control frame. But MAC receiver interprets and process flow control frames. Default is 0 SS - Spanning tree state Default is 11 00 - Blocking: Frame is dropped 01 - Listening: Frame is dropped 10 - Learning: Frame is dropped. Source MAC address is learned. 11 - Forwarding: Frame is forwarded. Source MAC address is learned. Bit [7:6] * * * * * 12.2.2 * * ECR2Pn: Port N Control Register I2C Address: 01B-035; CPU Address:0001+2xN Accessed by and serial interface and I2C (R/W) 7 6 5 4 3 Reserve 2 DisL 1 Ftf 0 Futf QoS Sel Bit[0]: * Filter untagged frame (Default 0) * 0: Disable * 1: All untagged frames from this port are discarded Bit[1]: * Filter Tag frame (Default 0) * 0: Disable * 1: All tagged frames from this port are discarded Bit[2]: * Learning Disable (Default 0) * 1 Learning is disabled on this port * 0 Learning is enabled on this port Bit[3]: * Must be set to `1' 40 Zarlink Semiconductor Inc. Data Sheet Bit [5:4:] * * * ZL50415 QOS mode selection (Default 00) Determines which of the 4 sets of QoS settings is used for 10/100 ports. Note that there are 4 sets of per-queue byte thresholds, and 4 sets of WFQ ratios programmed. These bits select among the 4 choices for each 10/100 port. Refer to QoS Application Note. 00: select class byte limit set 0 and classes WFQ credit set 0 01: select class byte limit set 1 and classes WFQ credit set 1 10: select class byte limit set 2 and classes WFQ credit set 2 11: select class byte limit set 3 and classes WFQ credit set 3 Reserved * * * * Bit[7:6] * 12.3 12.3.1 * * Group 1 Address VLAN Group AVTCL - VLAN Type Code Register Low I2C Address 036; CPU Address:h100 Accessed by serial interface and I2C (R/W) Bit[7:0]: * VLANType_LOW: Lower 8 bits of the VLAN type code (Default 00) 12.3.2 * * AVTCH - VLAN Type Code Register High I2C Address 037; CPU Address:h101 Accessed by serial interface and I2C (R/W) Bit[7:0]: * VLANType_HIGH: Upper 8 bits of the VLAN type code (Default is 81) 12.3.3 * * PVMAP00_0 - Port 00 Configuration Register 0 I2C Address 038, CPU Address:h102) Accessed by serial interface and I2C (R/W) Bit[7:0]: * VLAN Mask for ports 7 to 0 (Default FF) This register indicates the legal egress ports. A "1" on bit 7 means that the packet can be sent to port 7. A "0" on bit 7 means that any packet destined to port 7 will be discarded. This register works with registers 1 to form a 16 bit mask to all egress ports. 12.3.4 * * PVMAP00_1 - Port 00 Configuration Register 1 I2C Address h39, CPU Address:h103 Accessed by serial interface and I2C (R/W) Bit[7:0]: * VLAN Mask for ports 15 to 8 (Default is FF) Zarlink Semiconductor Inc. 41 ZL50415 12.3.5 * * Data Sheet PVMAP00_3 - Port 00 Configuration Register 3 I2C Address h3b, CPU Address:h105) Accessed by serial interface and I2C (R/W) 7 FP en 6 Drop 5 Default priority 3 tx 2 0 Bit [2:0]: Bit [5:3]: Reserved (Default 7) Default Transmit priority. Used when Bit[7] = 1 (Default 0) * * * * * * * * 000 001 010 011 100 101 110 111 Transmit Priority Level 0 (Lowest) Transmit Priority Level 1 Transmit Priority Level 2 Transmit Priority Level 3 Transmit Priority Level 4 Transmit Priority Level 5 Transmit Priority Level 6 Transmit Priority Level 7 (Highest) Bit [6]: Default Discard priority (Default 0) * * 0 - Discard Priority Level 0 (Lowest) 1 - Discard Priority Level 7(Highest) Bit [7]: Enable Fix Priority (Default 0) * * 0 Disable fix priority. All frames are analyzed. Transmit Priority and Discard Priority are based on VLAN Tag, TOS field or Logical Port. 1 Transmit Priority and Discard Priority are based on values programmed in bit [6:3] 12.4 * * * * * * * * * * * * * * * Port Configuration Register PVMAP01_0,1,3 I2C Address h3C,3D,3E,3F; CPU Address:h106,107,108,109) (Port 1) PVMAP02_0,1,3 I2C Address h40,41,42,43; CPU Address:h10A, 10B, 10C, 10D) (Port 2) PVMAP03_0,1,3 I2C Address h44,45,46,47; CPU Address:h10E, 10F, 110, 111) (Port 3) PVMAP04_0,1,3 I2C Address h48,49,4A,4B; CPU Address:h112, 113, 114, 115) (Port 4) PVMAP05_0,1,3 I2C Address h4C,4D,4E,4F; CPU Address:h116, 117, 118, 119) (Port 5) PVMAP06_0,1,3 I2C Address h50,51,52,53; CPU Address:h11A, 11B, 11C, 11D) (Port 6) PVMAP07_0,1,3 I2C Address h54,55,56,57; CPU Address:h11E, 11F, 120, 121) (Port 7) PVMAP08_0,1,3 I2C Address h58,59,5A,5B; CPU Address:h122, 123, 124, 125) (Port 8) PVMAP09_0,1,3 I2C Address h5C,5D,5E,5F; CPU Address:h126, 127, 128, 129) (Port 9) PVMAP10_0,1,3 I2C Address h60,61,62,63; CPU Address:h12A, 12B, 12C, 12D) (Port 10) PVMAP11_0,1,3 I2C Address h64,65,66,67; CPU Address:h12E, 12F, 130, 131) (Port 11) PVMAP12_0,1,3 I2C Address h68,69,6A,6B; CPU Address:h132, 133, 134, 135) (Port 12) PVMAP13_0,1,3 I2C Address h6C,6D,6E,6F; CPU Address:h136, 137, 138, 139) (Port 13) PVMAP14_0,1,3 I2C Address h70,71,72,73; CPU Address:h13A, h13B, 13C, 13D) (Port 14) PVMAP15_0,1,3 I2C Address h74,75,76,77; CPU Address:h13E, 13F, 140, 141) (Port 15) 42 Zarlink Semiconductor Inc. Data Sheet 12.4.1 * * ZL50415 PVMODE I2C Address: h0A4, CPU Address:h170 Accessed by serial interface, and I2C (R/W) 7 5 4 SM0 3 2 DF 1 SL 0 Bit [0]: Bit [1]: * * * Reserved Must be `0' Slow learning * Same function as SE_OP MODE bit 7. Either bit can enable the function; both need to be turned off to disable the feature. Bit [2]: * Disable dropping frames with destination MAC addresses 0180C2000001 to 0180C200000F * 0: Drop all frames in the range * 1: Treats frames as multicast Bit [3]: Bit [4]: * * Reserved Support MAC address 0 * 0: MAC address 0 is not learned. * 1: MAC address 0 is learned. Bit [7:5]: * Reserved 12.4.2 * * TRUNK0_MODE- Trunk group 0 mode I2C Address h0A5; CPU Address:203 Accessed by serial interface and I2C (R/W) 7 4 3 2 1 0 Hash Select Port Select Bit [1:0]: * Port selection in unmanaged mode. Input pin TRUNK0 enable/disable trunk group 0. * * * * 00 01 10 11 Reserved Port 0 and 1 are used for trunk0 Port 0,1 and 2 are used for trunk0 Port 0,1,2 and 3 are used for trunk0 Bit [3:2] * Hash Select. The Hash selected is valid for Trunk 0, 1 and 2. (Default 00) * * * * 00 01 10 11 for Use Source and Destination Mac Address for hashing Use Source Mac Address for hashing Use Destination Mac Address for hashing Use source destination MAC address and ingress physical port number hashing Zarlink Semiconductor Inc. 43 ZL50415 12.4.3 * * Data Sheet TRUNK1_MODE - Trunk group 1 mode I2C Address h0A6; CPU Address:20B Accessed by serial interface and I2C (R/W) 7 2 1 0 Port Select Bit [1:0]: * Port selection in unmanaged mode. Input pin TRUNK1 enable/disable trunk group 1. * * * * 00 01 10 11 Reserved Port 4 and 5 are used for trunk1 Reserved Port 4,5,6 and 7 are used for trunk1 12.4.4 * * TX_AGE - Tx Queue Aging timer I2C Address: h07;CPU Address:h325 Accessed by serial interface (RW) 7 6 5 Tx Queue Agent 0 * * * Bit[5:0]: Unit of 100ms (Default 8) Disable transmission queue aging if value is zero. Aging timer for all ports and queues. For no packet loss flow control, this register must be set to 0. 12.5 12.5.1 * * * * Group 4 Address Search Engine Group AGETIME_LOW - MAC address aging time Low I2C Address h0A8; CPU Address:h400 Accessed by serial interface and I2C (R/W) Bit [7:0] Low byte of the MAC address aging timer. MAC address aging is enable/disable by boot strap TSTOUT9 12.5.2 * * * * * AGETIME_HIGH -MAC address aging time High I2C Address h0A9; CPU Address h401 Accessed by serial interface and I2C (R/W) Bit [7:0]: High byte of the MAC address aging timer. The default setting provide 300 seconds aging time. Aging time is based on the following equation: {AGETIME_TIME,AGETIME_LOW} X (# of MAC address entries in the memory x 100sec). Number of MAC entries = 32K when 1MB is used. Number of MAC entries = 64K when 2MB is used. 44 Zarlink Semiconductor Inc. Data Sheet 12.5.3 * * * ZL50415 SE_OPMODE - Search Engine Operation Mode CPU Address:h403 Accessed by serial interface (R/W) {SE_OPMODE} X(# of entries 100usec) 7 SL 6 DMS 5 0 Bit [5:0]: Bit [6]: * * Reserved Disable MCT speedup aging * 1 - Disable speedup aging when MCT resource is low. * 0 - Enable speedup aging when MCT resource is low. Bit [7]: * Slow Learning * 1- Enable slow learning. Learning is temporary disabled when search demand is high * 0 - Learning is performed independent of search demand 12.6 12.6.1 * Group 5 Address Buffer Control/QOS Group FCBAT - FCB Aging Timer I2C Address h0AA; CPU Address:h500 7 FCBAT 0 Bit [7:0]: * * FCB Aging time. Unit of 1ms. (Default FF) This function is for buffer aging control. It is used to configure the aging time, and can be enabled/ disabled through bootstrap pin. It is not recommended to use this function for normal operation. 12.6.2 * * QOSC - QOS Control I2C Address h0AB; CPU Address:h501 Accessed by serial interface and I2C (R/W) 7 Tos-d 6 Tos-p 5 4 VF1c 3 1 0 L Bit [0]: * QoS frame lost is OK. Priority will be available for flow control enabled source only when this bit is set (Default 0) Zarlink Semiconductor Inc. 45 ZL50415 Bit [4]: * Per VLAN Multicast Flow Control (Default 0) * 0 - Disable * 1 - Enable Data Sheet Bit [5]: Bit [6]: * * Reserved Select TOS bits for Priority (Default 0) * 0 - Use TOS [4:2] bits to map the transmit priority * 1 - Use TOS [7:5] bits to map the transmit priority Bit [7]: * Select TOS bits for Drop Priority (Default 0) * 0 - Use TOS[4:2] bits to map the drop priority * 1 - Use TOS[7:5] bits to map the drop priority 12.6.3 * * FCR - Flooding Control Register I2C Address h0AC; CPU Address:h502 Accessed by serial interface and I2C (R/W) 7 Tos 6 TimeBase 4 3 U2MR 0 Bit [3:0]: * U2MR: Unicast to Multicast Rate. Units in terms of time base defined in bits [6:4]. This is used to limit the amount of flooding traffic. The value in U2MR specifies how many packets are allowed to flood within the time specified by bit [6:4]. To disable this function, program U2MR to 0. (Default = 8) Bit [6:4]: * TimeBase: 000 = 100us 001 = 200us 010 = 400us 011 = 800us 100 = 1.6ms 101 = 3.2ms 110 = 6.4ms 111 = 100us (same as 000) * Bit [7]: * (Default = 000) Select VLAN tag or TOS (IP packets) to be preferentially picked to map transmit priority and drop priority (Default = 0). * 0 - Select VLAN Tag priority field over TOS * 1 - Select TOS over VLAN tag priority field 46 Zarlink Semiconductor Inc. Data Sheet 12.6.4 * * ZL50415 AVPML - VLAN Priority Map I2C Address h0AD; CPU Address:h503 Accessed by serial interface and I2C (R/W) 7 6 VP2 5 VP1 3 2 VP0 0 Registers AVPML, AVPMM, and AVPMH allow the eight VLAN priorities to map into eight internal level transmit priorities. Under the internal transmit priority, seven is highest priority where as zero is the lowest. This feature allows the user the flexibility of redefining the VLAN priority field. For example, programming a value of 7 into bit 2:0 of the AVPML register would map VLAN priority 0 into internal transmit priority 7. The new priority is used inside the ZL50415. When the packet goes out it carries the original priority. Bit [2:0]: Bit [5:3]: Bit [7:6]: * * * Priority when the VLAN tag priority field is 0 (Default 0) Priority when the VLAN tag priority field is 1 (Default 0) Priority when the VLAN tag priority field is 2 (Default 0) 12.6.5 * * AVPMM - VLAN Priority Map I2C Address h0AE, CPU Address:h504 Accessed by serial interface and I2C (R/W) 7 VP5 6 VP4 4 3 VP3 1 0 VP2 Map VLAN priority into eight level transmit priorities: Bit [0]: Bit [3:1]: Bit [6:4]: Bit [7]: * * * * Priority when the VLAN tag priority field is 2 (Default 0) Priority when the VLAN tag priority field is 3 (Default 0) Priority when the VLAN tag priority field is 4 (Default 0) Priority when the VLAN tag priority field is 5 (Default 0) 12.6.6 * * AVPMH - VLAN Priority Map I2C Address h0AF, CPU Address:h505 Accessed by serial interface and I2C (R/W) 7 VP7 5 4 VP6 2 1 0 VP5 Zarlink Semiconductor Inc. 47 ZL50415 Map VLAN priority into eight level transmit priorities: Bit [1:0]: Bit [4:2]: Bit [7:5]: * * * Priority when the VLAN tag priority field is 5 (Default 0) Priority when the VLAN tag priority field is 6 (Default 0) Priority when the VLAN tag priority field is 7 (Default 0) Data Sheet 12.6.7 * * TOSPML - TOS Priority Map I2C Address h0B0, CPU Address:h506 Accessed by serial interface and I2C (R/W) 7 TP2 6 5 TP1 3 2 TP0 0 Map TOS field in IP packet into eight level transmit priorities Bit [2:0]: Bit [5:3]: Bit [7:6]: * * * Priority when the TOS field is 0 (Default 0) Priority when the TOS field is 1 (Default 0) Priority when the TOS field is 2 (Default 0) 12.6.8 * * TOSPMM - TOS Priority Map I2C Address h0B1, CPU Address:h507 Accessed by serial interface and I2C (R/W) 7 TP5 6 TP4 4 3 TP3 1 0 TP2 Map TOS field in IP packet into four level transmit priorities Bit [0]: Bit [3:1]: Bit [6:4]: Bit [7]: * * * * Priority when the TOS field is 2 (Default 0) Priority when the TOS field is 3 (Default 0) Priority when the TOS field is 4 (Default 0) Priority when the TOS field is 5 (Default 0) 48 Zarlink Semiconductor Inc. Data Sheet 12.6.9 * * ZL50415 TOSPMH - TOS Priority Map I2C Address h0B2, CPU Address:h508 Accessed by serial interface and I2C (R/W) 7 TP7 5 4 TP6 2 1 0 TP5 Map TOS field in IP packet into four level transmit priorities: Bit [1:0]: Bit [4:2]: Bit [7:5]: * * * Priority when the TOS field is 5 (Default 0) Priority when the TOS field is 6 (Default 0) Priority when the TOS field is 7 (Default 0) 12.6.10 * * AVDM - VLAN Discard Map I2C Address h0B3, CPU Address:h509 Accessed by serial interface and I2C (R/W) 7 FDV7 6 FDV6 5 FDV5 4 FDV4 3 FDV3 2 FDV2 1 FDV2 0 FDV0 Map VLAN priority into frame discard when low priority buffer usage is above threshold Bit [0]: Bit [1]: Bit [2]: Bit [3]: Bit [4]: Bit [5]: Bit [6]: Bit [7]: * * * * * * * * Frame drop priority when VLAN tag priority field is 0 (Default 0) Frame drop priority when VLAN tag priority field is 1 (Default 0) Frame drop priority when VLAN tag priority field is 2 (Default 0) Frame drop priority when VLAN tag priority field is 3 (Default 0) Frame drop priority when VLAN tag priority field is 4 (Default 0) Frame drop priority when VLAN tag priority field is 5 (Default 0) rame drop priority when VLAN tag priority field is 6 (Default 0) Frame drop priority when VLAN tag priority field is 7 (Default 0) Zarlink Semiconductor Inc. 49 ZL50415 12.6.11 * * Data Sheet TOSDML - TOS Discard Map I2C Address h0B4, CPU Address:h50A Accessed by serial interface and I2C (R/W) 7 FDT7 6 FDT6 5 FDT5 4 FDT4 3 FDT3 2 FDT2 1 FDT1 0 FDT0 Map TOS into frame discard when low priority buffer usage is above threshold Bit [0]: Bit [1]: Bit [2]: Bit [3]: Bit [4]: Bit [5]: Bit [6]: Bit [7]: * * * * * * * * Frame drop priority when TOS field is 0 (Default 0) Frame drop priority when TOS field is 1 (Default 0) Frame drop priority when TOS field is 2 (Default 0) Frame drop priority when TOS field is 3 (Default 0) Frame drop priority when TOS field is 4 (Default 0) Frame drop priority when TOS field is 5 (Default 0) Frame drop priority when TOS field is 6 (Default 0) Frame drop priority when TOS field is 7 (Default 0) 12.6.12 * * BMRC - Broadcast/Multicast Rate Control I2C Address h0B5, CPU Address:h50B) Accessed by serial interface and I2C (R/W) 7 Broadcast Rate 4 3 Multicast Rate 0 * This broadcast and multicast rate defines for each port the number of packet allowed to be forwarded within a specified time. Once the packet rate is reached, packets will be dropped. To turn off the rate limit, program the field to 0. Timebase is based on register 502 [6:4]. Bit [3:0] : * Multicast Rate Control Number of multicast packets allowed within the time defined in bits 6 to 4 of the Flooding Control Register (FCR). (Default 0). Broadcast Rate Control Number of broadcast packets allowed within the time defined in bits 6 to 4 of the Flooding Control Register (FCR). (Default 0) Bit [7:4] : * 50 Zarlink Semiconductor Inc. Data Sheet 12.6.13 * * ZL50415 UCC - Unicast Congestion Control I2C Address h0B6, CPU Address: 50C Accessed by serial interface and I2C (R/W) 7 Unicast congest threshold 0 Bit [7:0] : * Number of frame count. Used for best effort dropping at B% when destination port's best effort queue reaches UCC threshold and shared pool is all in use. Granularity 1 frame. (Default: h10 for 2 MB or h08 for 1 MB) 12.6.14 * * MCC - Multicast Congestion Control I2C Address h0B7, CPU Address: 50D Accessed by serial interface and I2C (R/W) 7 FC reaction prd 5 4 Multicast congest threshold 0 Bit [4:0]: * In multiples of two. Used for triggering MC flow control when destination multicast port's best effort queue reaches MCC threshold.(Default 0x10) Flow control reaction period (Default 2) Granularity 4uSec. Bit [7:5]: * Zarlink Semiconductor Inc. 51 ZL50415 12.6.15 * * Data Sheet PR100 - Port Reservation for 10/100 ports I2C Address h0B8, CPU Address 50E Accessed by serial interface and I2C (R/W) 7 Buffer low thd 4 3 0 SP Buffer reservation Bit [3:0]: * * Per port buffer reservation. Define the space in the FDB reserved for each 10/100 port. Expressed in multiples of 4 packets. For each packet 1536 bytes are reserved in the memory. Expressed in multiples of 4 packets. Threshold for dropping all best effort frames when destination port best efforts queues reach UCC threshold and shared pool all used and source port reservation is at or below the PR100[7:4] level. Also the threshold for initiating UC flow control. Default: - h58 for configuration with 2MB; - h35 for configuration with 1MB; Bits [7:4]: * * 12.6.16 * * SFCB - Share FCB Size I2C Address h0BA), CPU Address 510 Accessed by serial interface and I2C (R/W) 7 Shared buffer size 0 Bits [7:0]: * * Expressed in multiples of 4 packets. Buffer reservation for shared pool. Default: - hE6 for configuration with memory of 2MB; - h46 for configuration with memory of 1MB; 12.6.17 * * C2RS - Class 2 Reserve Size I2C Address h0BB, CPU Address 511 Accessed by serial interface and I2C (R/W) 7 Class 2 FCB Reservation 0 * Buffer reservation for class 2 (third lowest priority). Granularity 1. (Default 0) 52 Zarlink Semiconductor Inc. Data Sheet 12.6.18 * * ZL50415 C3RS - Class 3 Reserve Size I2C Address h0BC, CPU Address 512 Accessed by serial interface and I2C (R/W) 7 Class 3 FCB Reservation 0 * Buffer reservation for class 3. Granularity 1. (Default 0) 12.6.19 * * C4RS - Class 4 Reserve Size I2C Address h0BD, CPU Address 513 Accessed by serial interface and I2C (R/W) 7 Class 4 FCB Reservation 0 * Buffer reservation for class 4. Granularity 1. (Default 0) 12.6.20 * * C5RS - Class 5 Reserve Size I2C Address h0BE; CPU Address 514 Accessed by serial interface and I2C (R/W) 7 Class 5 FCB Reservation 0 * Buffer reservation for class 5. Granularity 1. (Default 0) 12.6.21 * * C6RS - Class 6 Reserve Size I2C Address h0BF; CPU Address 515 Accessed by serial interface and I2C (R/W) 7 Class 6 FCB Reservation 0 * Buffer reservation for class 6 (second highest priority). Granularity 1. (Default 0) 12.6.22 * * I 2C C7RS - Class 7 Reserve Size Address h0C0; CPU Address 516 Accessed by serial interface and I2C (R/W) 7 Class 7 FCB Reservation 0 * Buffer reservation for class 7 (highest priority). Granularity 1. (Default 0) Zarlink Semiconductor Inc. 53 ZL50415 12.6.23 * Data Sheet Classes Byte Limit Set 0 Accessed by serial interface and I2C (R/W): C -- QOSC00 - BYTE_C01 (I2C Address h0C1, CPU Address 517) B -- QOSC01 - BYTE_C02 (I2C Address h0C2, CPU Address 518) A -- QOSC02 - BYTE_C03 (I2C Address h0C3, CPU Address 519) QOSC00 through QOSC02 represents one set of values A-C for a 10/100 port when using the Weighted Random Early Drop (WRED) Scheme described in Chapter 7.7. There are four such sets of values A-C specified in Classes Byte Limit Set 0, 1, 2, and 3. Each 10/ 100 port can choose one of the four Byte Limit Sets as specified by the QoS Select field located in bits 5 to 4 of the ECR2n register. The values A-C are per-queue byte thresholds for random early drop. QOSC02 represents A, and QOSC00 represents C. Granularity when Delay bound is used: QOSC02: 128 bytes, QOSC01: 256 bytes. QOSC00: 512 bytes. Granularity when WFQ is used: QOSC02: 512 bytes, QOSC01: 512 bytes, QOSC00: 512 bytes. 12.6.24 * Classes Byte Limit Set 1 Accessed by serial interface and I2C (R/W): C - QOSC03 - BYTE_C11 (I2C Address h0C4, CPU Address 51a) B - QOSC04 - BYTE_C12 (I2C Address h0C5, CPU Address 51b) A - QOSC05 - BYTE_C13 (I2C Address h0C6, CPU Address 51c) QOSC03 through QOSC05 represents one set of values A-C for a 10/100 port when using the Weighted Random Early Detect (WRED) Scheme. Granularity when Delay bound is used: QOSC05: 128 bytes, QOSC04: 256 bytes. QOSC03: 512 bytes. Granularity when WFQ is used: QOSC05: 512 bytes, QOSC04: 512 bytes, QOSC03: 512 bytes. 12.6.25 * Classes Byte Limit Set 2 Accessed by serial interface and I2C (R/W): C - QOSC06 - BYTE_C21 (CPU Address 51d) B - QOSC07 - BYTE_C22 (CPU Address 51e) A - QOSC08 - BYTE_C23 (CPU Address 51f) QOSC06 through QOSC08 represents one set of values A-C for a 10/100 port when using the Weighted Random Early Detect (WRED) Scheme. Granularity when Delay bound is used: QOSC08: 128 bytes, QOSC07: 256 bytes. QOSC06: 512 bytes. Granularity when WFQ is used: QOSC08: 512 bytes, QOSC07: 512 bytes, QOSC06: 512 bytes. 12.6.26 * Classes Byte Limit Set 3 Accessed by serial interface and I2C (R/W): C - QOSC09 - BYTE_C31 (CPU Address 520) B - QOSC10 - BYTE_C32 (CPU Address 521) A - QOSC11 - BYTE_C33 (CPU Address 522) QOSC09 through QOSC011 represents one set of values A-C for a 10/100 port when using the Weighted Random Early Detect (WRED) Scheme. Granularity when Delay bound is used: QOSC11: 128 bytes, QOSC10: 256 bytes. QOSC09: 512 bytes. Granularity when WFQ is used: QOSC11: 512 bytes, QOSC10: 512 bytes, QOSC09: 512 bytes. 54 Zarlink Semiconductor Inc. Data Sheet 12.6.27 * ZL50415 Classes WFQ Credit Set 0 Accessed by serial interface (R/W) W3 - QOSC24[5:0] - CREDIT_C00 (CPU Address 52f) W2 - QOSC25[5:0] - CREDIT_C01 (CPU Address 530) W1 - QOSC26[5:0] - CREDIT_C02 (CPU Address 531) W0 - QOSC27[5:0] - CREDIT_C03 (CPU Address 532) QOSC24 through QOSC27 represents one set of WFQ parameters for a 10/100 port. There are four such sets of values. The granularity of the numbers is 1, and their sum must be 64. QOSC27 corresponds to W0, and QOSC24 corresponds to W3. * QOSC24[7:6]: Priority service type for the ports select this parameter set. Option 1 to 4. * QOSC25[7]: Priority service allow flow control for the ports select this parameter set. * QOSC25[6]: Flow control pause best effort traffic only Both flow control allow and flow control best effort only can take effect only the priority type is WFQ. 12.6.28 * Classes WFQ Credit Set 1 Accessed by serial interface (R/W) W3 - QOSC28[5:0] - CREDIT_C10 (CPU Address 533) W2 - QOSC29[5:0] - CREDIT_C11 (CPU Address 534) W1 - QOSC30[5:0] - CREDIT_C12 (CPU Address 535) W0 - QOSC31[5:0] - CREDIT_C13 (CPU Address 536) QOSC28 through QOSC31 represents one set of WFQ parameters for a 10/100 port. There are four such sets of values. The granularity of the numbers is 1, and their sum must be 64. QOSC31 corresponds to W0, and QOSC28 corresponds to W3. * * * QOSC28[7:6]: Priority service type for the ports select this parameter set. Option 1 to 4. QOSC29[7]: Priority service allow flow control for the ports select this parameter set. QOSC29[6]: Flow control pause best effort traffic only 12.6.29 * Classes WFQ Credit Set 2 Accessed by serial interface (R/W) W3 - QOSC32[5:0] - CREDIT_C20 (CPU Address 537) W2 - QOSC33[5:0] - CREDIT_C21 (CPU Address 538) W1 - QOSC34[5:0] - CREDIT_C22 (CPU Address 539) W0 - QOSC35[5:0] - CREDIT_C23 (CPU Address 53a) QOSC35 through QOSC32 represents one set of WFQ parameters for a 10/100 port. There are four such sets of values. The granularity of the numbers is 1, and their sum must be 64. QOSC35 corresponds to W0, and QOSC32 corresponds to W3. * * * QOSC32[7:6]: Priority service type for the ports select this parameter set. Option 1 to option 4. QOSC33[7]: Priority service allow flow control for the ports select this parameter set. QOSC33[6]: Flow Control pause best effort traffic only Zarlink Semiconductor Inc. 55 ZL50415 12.6.30 * Data Sheet Classes WFQ Credit Set 3 Accessed by serial interface (R/W) W3 - QOSC36[5;0] - CREDIT_C30 (CPU Address 53b) W2 - QOSC37[5:0] - CREDIT_C31 (CPU Address 53c) W1 - QOSC38[5:0] - CREDIT_C32 (CPU Address 53d) W0 - QOSC39[5:0] - CREDIT_C33 (CPU Address 53e) QOSC39 through QOSC36 represents one set of WFQ parameters for a 10/100 port. There are four such sets of values. The granularity of the numbers is 1, and their sum must be 64. QOSC39 corresponds to W0, and QOSC36 corresponds to W3. * * * QOSC36[7:6]: Priority service type for the ports select this parameter set. Option 1 to option 4. QOSC37[7]: Priority service allow flow control for the ports select this parameter set. QOSC37[6]: Flow Control pause best effort traffic only 12.6.31 * * RDRC0 - WRED Rate Control 0 I2C Address 0FB, CPU Address 553 Accessed by serial Interface and IcC (R/W) 7 X Rate 4 3 Y Rate 0 Bits [7:4]: Bits[3:0]: * * Corresponds to the frame drop percentage X% for WRED. Granularity 6.25%. Corresponds to the frame drop percentage Y% for WRED. Granularity 6.25%. See Programming QoS Registers application note for more information. 12.6.32 * * RDRC1 - WRED Rate Control 1 I2C Address 0FC, CPU Address 554 Accessed by serial Interface and I2C (R/W) 7 Z Rate 4 3 B Rate 0 Bits [7:4]: Bits[3:0]: * * Corresponds to the frame drop percentage Z% for WRED. Granularity 6.25%. Corresponds to the best effort frame drop percentage B%, when shared pool is all in use and destination port best effort queue reaches UCC. Granularity 6.25%. See Programming QoS Register application note for more information. 56 Zarlink Semiconductor Inc. Data Sheet 12.6.33 User Defined Logical Ports and Well Known Ports ZL50415 The ZL50415 supports classifying packet priority through layer 4 logical port information. It can be setup by 8 Well Known Ports, 8 User Defined Logical Ports, and 1 User Defined Range. The 8 Well Known Ports supported are: * * * * * * * * 0:23 1:512 2:6000 3:443 4:111 5:22555 6:22 7:554 Their respective priority can be programmed via Well_Known_Port [7:0] priority register. Well_Known_Port_ Enable can individually turn on/off each Well Known Port if desired. Similarly, the User Defined Logical Port provides the user programmability to the priority, plus the flexibility to select specific logical ports to fit the applications. The 8 User Logical Ports can be programmed via User_Port 0-7 registers. Two registers are required to be programmed for the logical port number. The respective priority can be programmed to the User_Port [7:0] priority register. The port priority can be individually enabled/disabled via User_Port_Enable register. The User Defined Range provides a range of logical port numbers with the same priority level. Programming is similar to the User Defined Logical Port. Instead of programming a fixed port number, an upper and lower limit need to be programmed, they are: {RHIGHH, RHIGHL} and {RLOWH, RLOWL} respectively. If the value in the upper limit is smaller or equal to the lower limit, the function is disabled. Any IP packet with a logical port that is less than the upper limit and more than the lower limit will use the priority specified in RPRIORITY. 12.6.33.1 USER_PORT0_(0~7) - USER DEFINE LOGICAL PORT (0~7) * * * * * * * * * USER_PORT_0 - I2C Address h0D6 + 0DE; CPU Address 580(Low) + 581(High) USER_PORT_1 - I2C Address h0D7 + 0DF; CPU Address 582 + 583 USER_PORT_2 - I2C Address h0D8 + 0E0; CPU Address 584 + 585 USER_PORT_3 - I2C Address h0D9 + 0E1; CPU Address 586 + 587 USER_PORT_4 - I2C Address h0DA + 0E2; CPU Address 588 + 589 USER_PORT_5 - I2C Address h0DB + 0E3; CPU Address 58a + 58b USER_PORT_6 - I2C Address h0DC + 0E4; CPU Address 58c + 58d USER_PORT_7 - I2C Address h0DD + 0E5; CPU Address 58e + 58f Accessed by serial interface and I2C (R/W) 7 TCP/UDP Logic Port Low 0 7 TCP/UDP Logic Port High * 0 (Default 00) This register is duplicated eight times from PORT 0 through PORT 7 and allows the definition of eight separate ports. Zarlink Semiconductor Inc. 57 ZL50415 12.6.33.2 USER_PORT_[1:0]_PRIORITY - User Define Logic Port 1 and 0 Priority * * I2C Address h0E6, CPU Address 590 Accessed by serial interface and I2C (R/W) 7 Priority 1 * 5 4 Drop 3 Priority 0 1 0 Drop Data Sheet The chip allows the definition of the priority Bits[3:0]: Bits [7:4]: * * Priority setting, transmission + dropping, for logic port 0 Priority setting, transmission + dropping, for logic port 1 (Default 00) 12.6.33.3 USER_PORT_[3:2]_PRIORITY - USER DEFINE LOGIC PORT 3 AND 2 PRIORITY * * I2C Address h0E7, CPU Address 591 Accessed by serial interface and I2C (R/W) 7 Priority 3 5 4 Drop 3 Priority 2 1 0 Drop 12.6.33.4 USER_PORT_[5:4]_PRIORITY - User Define Logic Port 5 and 4 Priority * * I2C Address h0E8, CPU Address 592 Accessed by serial interface and I2C (R/W) 7 Priority 5 * (Default 00) 5 4 Drop 3 Priority 4 1 0 Drop 12.6.33.5 USER_PORT_[7:6]_PRIORITY - User Define Logic Port 7 and 6 Priority * * I2C Address h0E9, CPU Address 593 Accessed by serial interface and I2C (R/W) 7 Priority 7 * (Default 00) 5 4 Drop 3 Priority 6 1 0 Drop 12.6.33.6 USER_PORT_ENABLE [7:0] - User Define Logic 7 to 0 Port Enables * * I2C Address h0EA, CPU Address 594 Accessed by serial interface and I2C (R/W) 7 P7 * (Default 00) 6 P6 5 P5 4 P4 3 P3 2 P2 1 P1 0 P0 58 Zarlink Semiconductor Inc. Data Sheet I2C Address h0EB, CPU Address 595 Accessed by serial interface and I2C (R/W) 7 Priority 1 * * * 5 4 Drop 3 Priority 0 1 0 Drop ZL50415 12.6.33.7 WELL_KNOWN_PORT [1:0] PRIORITY- Well Known Logic Port 1 and 0 Priority * * Priority 0 - Well known port 23 for telnet applications. Priority 1 - Well known port 512 for TCP/UDP (Default 00) 12.6.33.8 WELL_KNOWN_PORT [3:2] PRIORITY- WELL KNOWN LOGIC PORT 3 AND 2 PRIORITY * * I2C Address h0EC, CPU Address 596 Accessed by serial interface and I2C (R/W) 7 Priority 3 * * * 5 4 Drop 3 Priority 2 1 0 Drop Priority 2 - Well known port 6000 for XWIN. Priority 3 - Well known port 443 for http. sec (Default 00) 12.6.33.9 WELL_KNOWN_PORT [5:4] PRIORITY- WELL KNOWN LOGIC PORT 5 AND 4 PRIORITY * * I2C Address h0ED, CPU Address 597 Accessed by serial interface and I2C (R/W) 7 Priority 5 * * * 5 4 Drop 3 Priority 4 1 0 Drop Priority 4 - Well known port 111 for sun rpe. Priority 5 - Well known port 22555 for IP Phone call setup. (Default 00) 12.6.33.10 WELL_KNOWN_PORT [7:6] PRIORITY- WELL KNOWN LOGIC PORT 7 AND 6 PRIORITY * * I2C Address h0EE, CPU Address 598 Accessed by serial interface and I2C (R/W) 7 Priority 7 * * * 5 4 Drop 3 Priority 6 1 0 Drop Priority 6 - Well known port 22 for ssh. Priority 7 - Well known port 554 for rtsp. (Default 00) Zarlink Semiconductor Inc. 59 ZL50415 I2C Address h0EF, CPU Address 599 Accessed by serial interface and I2C (R/W) 7 P7 * 1 - Enable * 0 - Disable Data Sheet 12.6.33.11 WELL KNOWN_PORT_ENABLE [7:0] - WELL KNOWN LOGIC 7 TO 0 PORT ENABLES * * 6 P6 5 P5 4 P4 3 P3 2 P2 1 P1 0 P0 * (Default 00) RLOWL - User Define Range Low Bit 7:0 * * * I2C Address h0F4, CPU Address: 59a Accessed by serial interface and I2C (R/W) (Default 00) 12.6.33.12 RLOWH - USER DEFINE RANGE LOW BIT 15:8 * * * I2C Address h0F5, CPU Address: 59b Accessed by serial interface and I2C (R/W) (Default 00) 12.6.33.13 RHIGHL - USER DEFINE RANGE HIGH BIT 7:0 * * * I2C Address h0D3, CPU Address: 59c Accessed by serial interface and I2C (R/W) (Default 00) 12.6.33.14 RHIGHH - USER DEFINE RANGE HIGH BIT 15:8 * * * I2C Address h0D4, CPU Address: 59d Accessed by serial interface and I2C (R/W) (Default 00) 12.6.33.15 RPRIORITY - USER DEFINE RANGE PRIORITY * * I2C Address h0D5, CPU Address: 59e Accessed by serial interface and I2C (R/W) 7 4 3 1 0 Drop Range Transmit Priority * RLOW and RHIGH form a range for logical ports to be classified with priority specified in RPRIORITY. Bit[3:1] Bits[0]: * * Transmit Priority Drop Priority 60 Zarlink Semiconductor Inc. Data Sheet 12.7 12.7.1 * * ZL50415 Group 6 Address MISC Group MII_OP0 - MII Register Option 0 I2C Address F0, CPU Address:h600 Accessed by serial interface and I2C (R/W) 7 hfc 6 1prst 5 DisJ 4 Vendor Spc. Reg Addr 0 Bits [7]: * Half duplex flow control feature * 0 = Half duplex flow control always enable * 1 = Half duplex flow control by negotiation Bits[6]: Bits[5]: * * Link partner reset auto-negotiate disable Disable jabber detection. This is for HomePNA application or any serial operation slower than 10Mbps. * 1 = disable * 0 = enable Bit[4:0]: * Vendor specified link status register address (null value means don't use it) (Default 00); used when the Linkup bit position in the PHY is non-standard. 12.7.2 * * MII_OP1 - MII Register Option 1 I2C Address F1, CPU Address:h601 Accessed by serial interface and I2C (R/W) 7 Speed bit location 4 3 Duplex bit location 0 Bits[3:0]: Bits [7:4]: * * Duplex bit location in vendor specified register Speed bit location in vendor specified register (Default 00) Zarlink Semiconductor Inc. 61 ZL50415 12.7.3 * * Data Sheet FEN - Feature Register I2C Address F2, CPU Address:h602 Accessed by serial interface and I2C (R/W) 7 DML 6 MII 5 3 2 DS 1 0 Bits [1:0]: Bit [2]: * * * * * Reserved (Default 0) Support DS EF Code. (Default 0) When 101110 is detected in DS field (TOS [7:2]), the frame priority is set for 110 and drop is set for 0. Reserved (Default 010) Disable MII Management State Machine * 0: Enable MII Management State Machine (Default 0) * 1: Disable MII Management State Machine Bit [5:3]: Bit [6]: Bit [7]: * Disable using MCT link list structure * 0: Enable using MCT Link List structure (Default 0) * 1: Disable using MCT Link List structure 12.7.4 * * * MIIC0 - MII Command Register 0 CPU Address:h603 Accessed by serial interface only (R/W) Bit [7:0] MII Data [7:0] Note: Before programming MII command: set FEN[6], check MIIC3, making sure no RDY, and no VALID; then program MII command. 12.7.5 * * * MIIC1 - MII Command Register 1 CPU Address:h604 Accessed by serial interface only (R/W) Bit [7:0] MII Data [15:8] Note: Before programming MII command: set FEN[6], check MIIC3, making sure no RDY and no VALID; then program MII command. 62 Zarlink Semiconductor Inc. Data Sheet 12.7.6 * * ZL50415 MIIC2 - MII Command Register 2 CPU Address:h605 Accessed by serial interface only (R/W) 7 6 Mii OP 5 4 Register address 0 Bits [4:0]: Bit [6:5] * * REG_AD - Register PHY Address OP - Operation code "10" for read command and "01" for write command Note: Before programming MII command: set FEN[6], check MIIC3, making sure no RDY and no VALID; then program MII command. Writing to this register will initiate a serial management cycle to the MII management interface. For detail information, please refer to the PHY Control Application Note. 12.7.7 * * MIC3 - MII Command Register 3 CPU Address:h606 Accessed by serial interface only (R/W) 7 Rdy 6 Valid 5 4 Phy address 0 Bits [4:0]: Bit [6] Bit [7] * * * PHY_AD - 5 Bit PHY Address VALID - Data Valid from PHY (Read Only) RDY - Data is returned from PHY (Ready Only) Note: Before programming MII command: set FEN[6], check MIIC3, making sure no RDY and no VALID; then program MII command. 12.7.8 * * * MIID0 - MII Data Register 0 CPU Address:h607 Accessed by serial interface only (RO) Bit [7:0] MII Data [7:0] 12.7.9 * * * MIID1 - MII Data Register 1 CPU Address:h608 Accessed by serial interface only (RO) Bit [7:0] MII Data [15:8] Zarlink Semiconductor Inc. 63 ZL50415 12.7.10 * * Data Sheet LED Mode - LED Control CPU Address:h609 Accessed by serial interface and I2C (R/W) 7 5 4 Clock rate 3 2 Hold Time 1 0 Bit [0] Bit[2:1]: * * Reserved (Default 0) Hold time for LED signal (Default= 00) 00=8msec 10=32msec 01=16msec 11=64msec Bit[4:3]: * " LED clock frequency (Default 0) 00=100M/8=12.5 MHz 10=100M/32= 125 MHz 01=100M/16= 25 MHz 11=100M/64=1.5625 MHz Bit[7:5]: * Reserved. Must be 0. (Default 0) 12.7.11 * * CHECKSUM - EEPROM Checksum I2C Address FF, CPU Address:h60b Accessed by serial interface and I2C (R/W) Bit [7:0]: * (Default 0) Before requesting that the ZL50415 updates the EEPROM device, the correct checksum needs to be calculated and written into this checksum register. When the ZL50415 boots from the EEPROM the checksum is calculated and the value must be zero. If the checksum is not zeroed the ZL50415 does not start and pin CHECKSUM_OK is set to zero. The checksum formula is: FF I2C register = 0 I=0 64 Zarlink Semiconductor Inc. Data Sheet 12.8 12.8.1 * * ZL50415 Group 7 Address Port Mirroring Group MIRROR1_SRC - Port Mirror source port CPU Address 700 Accessed by serial interface (R/W) (Default 7F) 7 OV 6 5 I/O 4 Src Port Select 0 Bit [4:0]: Bit [5]: Bit [7]: * * * * Source port to be mirrored. Use illegal port number to disable mirroring 1 - select ingress data 0 - select egress data Must be `1' 12.8.2 * * MIRROR1_DEST - Port Mirror destination CPU Address 701 Accessed by serial interface (R/W) (Default 17) 7 5 4 Dest Port Select 0 Bit [4:0]: * Port Mirror Destination 12.8.3 * * MIRROR2_SRC - Port Mirror source port CPU Address 702 Accessed by serial interface (R/W) (Default FF) 7 6 5 I/O 4 Src Port Select 0 Bit [4:0]: Bit [5]: Bit [7] * * * * Source port to be mirrored. Use illegal port number to disable mirroring 1 - select ingress data 0 - select egress data Must be 1 Zarlink Semiconductor Inc. 65 ZL50415 12.8.4 * * Data Sheet MIRROR2_DEST - Port Mirror destination CPU Address 703 Accessed by serial interface (R/W) (Default 00) 7 5 4 Dest Port Select 0 Bit [4:0]: * Port Mirror Destination 12.9 12.9.1 * * Group F Address CPU Access Group GCR-Global Control Register CPU Address: hF00 Accessed by serial interface. (R/W) 7 4 3 Reset 2 Bist 1 SR 0 SC Bit [0]: Bit[1]: Bit[2]: * * * * * * * * * Store configuration (Default = 0) Write `1' followed by `0' to store configuration into external EEPROM Store configuration and reset (Default = 0) Write `1' to store configuration into external EEPROM and reset chip Start BIST (Default = 0) Write `1' followed by `0' to start the device's built-in self-test. The result is found in the DCR register. Soft Reset (Default = 0) Write `1' to reset chip Reserved. Bit[3]: Bit[4]: 66 Zarlink Semiconductor Inc. Data Sheet 12.9.2 * * ZL50415 DCR-Device Status and Signature Register CPU Address: hF01 Accessed by serial interface. (RO) 7 6 5 Signature 4 3 RE 2 BinP 1 BR 0 BW Revision Bit [0]: Bit[1]: Bit[2]: Bit[3]: Bit[5:4]: Bit [7:6]: * * * * * * * * * * * * * * 1: Busy writing configuration to I2C 0: Not busy writing configuration to I2C 1: Busy reading configuration from I2C 0: Not busy reading configuration from I2C 1: BIST in progress 0: BIST not running 1: RAM Error 0: RAM OK Device Signature 01: ZL50415 device Revision 00: Initial Silicon 01: XA1 Silicon 10: Production Silicon 12.9.3 * * DCR1-Chip status CPU Address: hF02 Accessed by serial interface (RO) 7 CIC 6 0 Bit [7] * Chip initialization completed Zarlink Semiconductor Inc. 67 ZL50415 12.9.4 * * Data Sheet DPST - Device Port Status Register CPU Address:hF03 Accessed by serial interface (R/W) Bit[4:0]: * Read back index register. This is used for selecting what to read back from DTST. (Default 00) - 5'b00000 - Port 0 Operating mode and Negotiation status - 5'b00001 - Port 1 Operating mode/Neg status - 5'b00010 - Port 2 Operating mode/Neg status - 5'b00011 - Port 3 Operating mode/Neg status - 5'b00100 - Port 4 Operating mode/Neg status - 5'b00101 - Port 5 Operating mode/Neg status - 5'b00110 - Port 6 Operating mode/Neg status - 5'b00111 - Port 7 Operating mode/Neg status - 5'b01000 - Port 8 Operating mode/Neg status - 5'b01001 - Port 9 Operating mode/Neg status - 5'b01010 - Port 10 Operating mode/Neg status - 5'b01011 - Port 11 Operating mode/Neg status - 5'b01100 - Port 12 Operating mode/Neg status - 5'b01101 - Port 13 Operating mode/Neg status - 5'b01110 - Port 14 Operating mode/Neg status - 5'b01111 - Port 15 Operating mode/Neg status - 5'b10XXX - Reserved 68 Zarlink Semiconductor Inc. Data Sheet 12.9.5 * * * ZL50415 DTST - Data read back register CPU Address: hF04 Accessed by serial interface (RO) This register provides various internal information as selected in DPST bit[4:0]. Refer to the PHY Control Application Note. 7 4 3 Inkdn 2 FE 1 Fdpx 0 FcEn When bit is 1: * * * * * Bit[0] - Flow control enable Bit[1] - Full duplex port Bit[2] - Fast Ethernet port Bit[3] - Link is down Bit[7:4] - Reserved 12.9.6 * * PLLCR - PLL Control Register CPU Address: hF05 Accessed by serial interface (RW) Bit[3]Must be '1' Bit[7]Selects strap option or LCLK/OECLK registers 0 - Strap option (default) 1 - LCLK/OECLK registers 12.9.7 * * LCLK - LA_CLK delay from internal OE_CLK CPU Address: hF06 Accessed by serial interface (RW) LCLK 80h 40h 20h 10h 08h 04h 02h 01h Delay 8 Buffers Delay 7 Buffers Delay 6 Buffers Delay 5 Buffers Delay (Recommend) 4 Buffers Delay 3 Buffers Delay 2 Buffers Delay 1 Buffers Delay PD[12:10] 000b 001b 010b 011b 100b 101b 110b 111b Zarlink Semiconductor Inc. 69 ZL50415 Data Sheet The LCLK delay from SCLK is the sum of the delay programmed in here and the delay in OECLK register. 12.9.8 * * OECLK - Internal OE_CLK delay from SCLK CPU Address: hF07 Accessed by serial interface (RW) The OE_CLK is used for generating the OE0 and OE1 signals. PD[15:13] 000b 001b 010b 011b 100b 101b 110b 111b OECLK 80h 40h 20h 10h 08h 04h 02h 01h Delay 8 Buffers Delay 7 Buffers Delay (Recommend) 6 Buffers Delay 5 Buffers Delay 4 Buffers Delay 3 Buffers Delay 2 Buffers Delay 1 Buffers Delay 12.9.9 * * * DA - DA Register CPU Address: hFFF Accessed by serial interface (RO) Always return 8'h DA. Indicate the serial port connection is good. 70 Zarlink Semiconductor Inc. Data Sheet 13.0 13.1 ZL50415 BGA and Ball Signal Descriptions BGA Views (TOP - View) 13.1.1 1 A 2 Encapsulated View 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 LA_D LA_D LA_D LA_D LA_D LA_A LA_O LA_A LA_A LA_A LA_A LA_D LA_D LA_D LA_D LA_D OE_ LA_ TRUN RESE RESE SCL 4 7 10 13 15 4 E0_ 8 13 16 19 33 36 39 42 45 CLK0 CLK0 K1 RVED RVED TO S D A S T R O T ST 7 BE U D0 TSTO TSTO UT8 UT3 B LA_D LA_D LA_D LA_D LA_D LA_D LA_A LA_O LA_A LA_A LA_A LA_A LA_D LA_D LA_D LA_D LA_D OE_ LA_ LA_D RESE RESE RESE RESE 1 3 6 9 12 14 DSC_ E1_ 7 12 15 18 32 35 38 41 44 CLK1 CLK1 62 RVED RVED RVED RVED C LA_C LA_D LA_D LA_D LA_D LA_D LA_A LA_O LA_W T_MO LA_A LA_A LA_A LA_A LA_D LA_D LA_D LA_D OE_ LA_ P_D TRUN RESE RESE AUTO TSTO TSTO TSTO TSTO LK 0 2 5 8 11 3 E_ E_ DE1 11 14 17 20 34 37 40 43 CLK2 CLK2 K0 RVED RVED FD UT11 UT9 UT4 UT0 D AGN LA_D LA_D LA_D LA_D LA_D LA_D LA_D LA_D LA_A LA_A LA_W LA_D LA_D LA_D LA_D LA_D LA_D LA_D LA_D LA_D SCAN SCAN TSTO TSTO TSTO TSTO TSTO TSTO D 17 19 21 23 25 27 29 31 6 10 E0_ 49 51 53 55 57 59 61 63 47 COL CLK UT14 UT13 UT12 UT10 UT5 UT1 AN S C A N T S T O R E S E R E S E S CO D T S T O T S T O LI N K U T15 R VED R VED ME UT6 UT2 RESE RESE RESE RESE RESE RVED RVED RVED RVED RVED RESE RESE RESE RESE RESE RVED RVED RVED RVED RVED RESE RESE RESE RESE RESE RVED RVED RVED RVED RVED RESE RESE RESE RESE RESE RVED RVED RVED RVED RVED VDD VDD VDD VDD RESE RESE RESE RESE RESE RVED RVED RVED RVED RVED RESE RESE RESE RESE RESE RVED RVED RVED RVED RVED VDD VSS VSS VSS VSS VSS VSS VSS VDD RESE RESE RESE RESE RESE RVED RVED RVED RVED RVED VCC RESE RVE D RESE VCC RVE D RESE VCC RVE D RESE VCC RVE D RESE RVED RESE RVED RESE RVED RESE RVED RES MDIO RVEE D MDC M_CL K _ _ _ _ _ _ _ _ A_W _ _ _ _ _ _ _ RES _ E S C L K L A 6 D L A 8 D L A 0 D L A 2 D L A 4 D L A 6 D L A 8 D L A 0 D L A _ A L A _ A LE 1 _ L A 8 D L A 0 D L A 2 D L A 4 D L A 6 D L A 8 D L A 0 D R V E E L A 6 D 1 1 2 2 2 2 2 3 5 9 4 5 5 5 5 5 6 D4 F AVC C RESI SCAN RESE RESE N_ EN RVED RVED VCC VCC VCC VCC VCC RES RESE RES RES RES G RVEE T OUT RVEE RVEE RVEE D D D D _ H RESE RESE RESE RESE RESE RVED RVED RVED RVED RVED J RESE RESE RESE RESE RESE RVED RVED RVED RVED RVED RESE RESE RESE RESE RESE K RVED RVED RVED RVED RVED L RESE RESE RESE RESE RESE RVED RVED RVED RVED RVED RESE RESE RESE RESE RESE M RVED RVED RVED RVED RVED RESE RESE RESE RESE RESE N RVED RVED RVED RVED RVE D E R E S E R E S E R E S E R E S E R E SE P RVED RVED RVED RVED RV D RES RES RES RES RESE R RVEE RVEE RVEE RVEE RVE D D D D D RESE RESE RESE RESE RESE T RVED RVED RVED RVED RVE D VCC VDD VSS VSS VSS VSS VSS VSS VSS VDD VCC VCC VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCC VSS VSS VSS VSS VSS VSS VSS RESE RESE RESE RESE RVED RVED RVED RVED RESE RESE T_MO RESE RESE U RVED RVED DE0 RVED RVE VCC D RESE RESE RESE RESE RESE V RVED RVED RVED RVED RVED RESE RESE RESE RESE RESE W RVED RVED RVED RVED RVED RES RES RES RES RES Y RVEE RVEE RVEE RVEE RVEE D D D D D A RESE RESE RESE RESE RESE A RVED RVED RVED RVED RVED A RESE RESE RESE RESE RESE B RVED RVED RVED RVED RVED A RESE RESE RESE RESE RESE C RVED RVED RVED RVED RVED A RESE RESE RESE RESE RESE D RVED RVED RVED RVED RVED VDD VSS VSS VSS VSS VSS VSS VSS VDD VCC RESE RESE RESE RESE RESE RVE RVED RVED RVED RVED D RESE RESE RESE RESE RESE RVED RVED RVED RVED RVED RESE RESE RESE RESE RESE RVED RVED RVED RVED RVED VDD VSS VSS VSS VSS VSS VSS VSS VDD VDD VDD VDD VDD RESE RESE RESE RESE RESE RVED RVED RVED RVED RVED RESE RESE RESE RESE RESE RVED RVED RVED RVED RVED RESE RESE RESE RESE RESE RVED RVED RVED RVED RVED RESE RESE RESE RESE RESE RVED RVED RVED RVED RVED VCC VCC VCC VCC VCC RESE RESE RESE RESE RESE RVED RVED RVED RVED RVED A M0_T M0_T M0_T M3_T M3_T M3_R M5_T M5_T M5_R M8_T M8_T M8_R M10_ M10_ M10_ M13_ RESE M15_ RESE M15_ M15_ RESE RESE RESE RESE RESE RESE RESE E XEN XD0 XD1 XD1 XEN XD0 XD1 XEN XD0 XD1 XEN XD0 TXD1 TXEN RXD0 TXD1 RVED TXD1 RVED TXEN RXD0 RVED RVED RVED RVED RVED RVED RVED A M0_R M0_R M0_C M3_T M3_C M3_R M5_T M5_C M5_R M8_T M8_C M8_R M10_ M10_ M10_ M13_ M13_ M13_ M14_ RESE M15_ RESE RESE RESE RESE RESE RESE RESE RESE RS XD0 RS XD1 XD0 RS XD1 XD0 RS XD1 TXD0 CRS RXD1 TXD0 CRS RXD1 CRS RVED RXD1 RVED RVED RVED RVED RVED RVED RVED RVED F XD1 XD0 A M1_T M1_T M1_T M2_T M2_C M4_T M4_C M6_T M6_C M7_T M7_C M9_T M9_C M11_ M11_ M12_ M12_ M14_ M15_ RESE RESE RESE RESE RESE RESE RESE RESE RESE RESE RS XD1 RS XD1 RS XD1 RS XD1 RS TXD1 CRS TXD1 CRS TXD1 TXD0 RVED RVED RVED RVED RVED RVED RVED RVED RVED RVED G XEN XD0 XD1 XD1 A H AJ 1 2 M1_R M1_C M2_T M2_R M4_T M4_R M6_T M6_R M7_T M7_R M9_T M9_R M11_ M11_ M12_ M12_ M14_ M14_ M13_ M15_ RESE RESE RESE RESE RESE RESE RESE XD0 RS XD0 XD0 XD0 XD0 XD0 XD0 XD0 XD0 XD0 XD0 TXD0 RXD0 TXD0 RXD0 TXD0 RXD0 RXD0 CRS RVED RVED RVED RVED RVED RVED RVED M1_R M2_T M2_R M4_T M4_R M6_T M6_R M7_T M7_R M9_T M9_R M11_ M11_ M12_ M12_ M14_ M14_ RESE M13_ RESE RESE RESE RESE RESE RESE XD1 XEN XD1 XEN XD1 XEN XD1 XEN XD1 XEN XD1 TXEN RXD1 TXEN RXD1 TXEN RXD1 RVED TXEN RVED RVED RVED RVED RVED RVED 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 Zarlink Semiconductor Inc. 71 ZL50415 13.1.2 Power and Ground Distribution Data Sheet The following figure provides an encapsulated view of the power and ground distribution 1 A 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 L A_D L A_D L A_D L A_D L A_D L A_A L A_O L A_A L A_A L A_A L A_A L A_D L A_D L A_D L A_D L A_D RE SE RE SE T RUN MIR R MIRR SCL 4 7 10 13 15 4 E0_ 8 13 16 19 33 36 39 42 45 R VED RVED K 1 OR4 OR1 SDA STRO TSTO BE UT7 D0 TSTO TSTO UT8 UT3 B L A_D L A_D L A_D L A_D L A_D L A_D L A_A L A_O L A_A L A_A L A_A L A_A L A_D L A_D L A_D L A_D L A_D RE SE RE SE L A_D MIR R MIRR TRUN RE SE 1 3 6 9 12 14 DSC_ E1_ 7 12 15 18 32 35 38 41 44 R VED RVED 6 2 OR5 OR2 K2 R VED C L A_C L A_D L A_D L A_D L A_D L A_D L A_A L A_O L A_W T_ MO L A_A L A_A L A_A L A_A L A_D L A_D L A _D L A_D RE SE RE SE RE SE TR U N M IR R MIR R A UT O T ST O T STO T STO T STO LK 0 2 5 8 11 3 E_ E_ DE1 11 14 17 20 34 37 40 43 R VED RVED RVED K0 OR3 OR0 FD UT11 UT9 UT4 UT0 D AGN L A_D L A_D L A_D L A_D L A_D L A_D L A_D L A_D L A_A L A_A L A_W L A_D L A_D L A_D L A_D L A_D L A_D L A_D L A_D L A_D SCAN S CAN T ST O T STO T ST O T STO T ST O T STO D 17 19 21 23 25 27 29 31 6 10 E0_ 49 51 53 55 57 59 61 63 47 COL CLK U T14 UT13 UT12 UT10 UT5 UT1 SCAN S CAN T ST O RE SE RE SE T ST O T STO MOD LINK U T15 R VED RVED UT6 UT2 E RE SE RE SE RE SE RE SE RE SE R VED RVED R VED RVED R VED RE SE RE SE RE SE RE SE RE SE R VED RVED R VED RVED R VED RE SE RE SE RE SE RE SE RE SE R VED RVED R VED RVED R VED RE SE RE SE RE SE RE SE RE SE R VED RVED R VED RVED R VED VDD VDD VDD VDD RE SE RE SE RE SE RE SE RE SE R VED RVED R VED RVED R VED RE SE RE SE RE SE RE SE RE SE R VED RVED R VED RVED R VED VDD VSS VSS VSS VSS VSS VSS VSS VDD VDD 33 RE SE RE SE RE SE RE SE RE SE R VED RVED R VED RVED R VED RE SE R VE D RE SE VDD R VE 33 D RE SE VDD R VE 33 D RE SE VDD R VE 33 D VDD 33 RE SE RE SE RE SE RE SE RVED R VED RVED R VED RESE RVED RESE RVED MDIO RE SE R VED MDC M_CL K L A_D LA_D L A_D LA_D L A_D LA_D L A_D LA_D L A_A LA_A LA_W LA_D LA_D LA_D LA_D LA_D LA_D LA_D RESE LA_D E SCLK 16 18 20 22 24 26 28 30 5 9 E1_ 48 50 52 54 56 58 6 0 RVED 4 6 AVC C RESI SC AN LB_D LB_D N_ EN 63 62 VDD VDD 33 33 VDD 33 VDD 33 VDD 33 RE SE LB_D LB_D LB_D LB_C G T OUT 47 61 60 LK _ H LB_D LB_D LB_D LB_D LB_D 46 45 44 59 58 LB_D LB_D LB_D LB_D LB_D 43 42 41 57 56 K LB_D LB_D LB_D LB_D LB_D 40 39 38 55 54 L LB_D LB_D LB_D LB_D LB_D 37 36 35 53 52 M LB_D LB_D LB_D LB_D LB_D 34 33 32 51 50 LB_A LB_A LB_A LB_D LB_D VDD 18 19 20 49 48 33 LB_A LB_A LB_A LB_W LB _ VDD 15 16 17 E0_ WE1_ 33 N VDD VSS VSS VSS VSS VSS VSS VSS VDD P VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS R LB_A LB_A LB_A LB_A LB_A VDD 10 11 12 13 14 33 T LB_A LB_A LB_A LB_A LB_A VDD 5 6 7 8 9 33 U LB_O LB_O T_ MO LB_D LB_D VDD E0_ E1_ DE0 31 30 33 VDD VSS VSS VSS VSS VSS VSS VSS RE SE RE SE RE SE RE SE RVED R VED RVED R VED VSS VSS VSS VSS VSS VSS VSS VDD RE SE RE SE RE SE RE SE RE SE R VE RVED R VED RVED R VED D RE SE RE SE RE SE RE SE RE SE R VED RVED R VED RVED R VED RE SE RE SE RE SE RE SE RE SE R VED RVED R VED RVED R VED LB_A LB_O LB _W LB_D LB_D V DSC_ E_ E_ 29 28 W LB_D LB_A LB_A LB_D LB_D 15 3 4 27 26 LB_D LB_D LB_D LB_D LB_D 14 13 12 25 24 VDD VSS VSS VSS VSS VSS VSS VSS VDD Y VDD VDD VDD VDD M25 _ M25_ M25 _ M25 _ M25 _ R XD6 TXD8 T XD9 RXD7 R XD8 M25 _ M25_ M25 _ M25 _ M25 _ T XD6 TXD7 R XD3 RXD4 R XD5 M25 _ M25_ M25 _ M25 _ M25 _ T XD4 TXD5 R XD0 RXD1 R XD2 M25 _ M25_ M23 _ M23 _ M23 _ T XD2 TXD3 C RS RXD0 R XD1 A LB_D LB_D LB_D LB_D LB_D 11 10 9 23 22 A A LB_D LB_D LB_D LB_D LB_D 8 7 6 21 20 B A LB_D LB_D LB_D LB_D LB_D 5 4 3 19 18 C A LB_D LB_D LB_D LB_D LB_D 2 1 0 17 16 D VDD VDD 33 33 VDD 33 VDD 33 VDD 33 M25 _ M25_ M23 _ M23 _ M23 _ T XD0 TXD1 T XD1 TXD0 T XEN A M0_T M0_T M0_T M3_T M3_T M3_R M5_T M5_T M5_ R M8_T M8_T M8_R M10 _ M10_ M10 _ M13_ RE SE M15_ RE SE M15_ M15 _ RE SE RE SE RE SE RE SE RE SE RE SE RE SE E XEN XD0 XD1 XD1 XEN XD0 XD1 XEN XD0 XD1 XEN XD0 TXD1 TXEN RXD0 TXD1 RVED TXD1 R VED TXEN RXD0 RVED R VED RVED R VED RVED R VED RVED F M0_ R M0_R M0_ C M3_T M3_ C M3_R M5_T M5_C M5_ R M8_T M8_ C M8_R M10 _ M10_ M10 _ M13_ M13 _ M13_ M14 _ RE SE M15 _ RE SE RE SE RE SE RE SE RE SE RE SE RE SE RE SE XD1 XD0 RS XD0 RS XD1 XD0 RS XD1 XD0 RS XD1 TXD0 CRS RXD1 TXD0 CRS RXD1 CRS RVED RXD1 RVED R VED RVED R VED RVED R VED RVED R VED A M1_T M1_T M1_T M2_T M2_ C M4_T M4_ C M6_T M6_ C M7_T M7_ C M9_T M9_ C M11_ M11 _ M12_ M12 _ M14_ M15 _ RE SE RE SE M18_ M18 _ M19_ M19 _ M21_ M21 _ M22 _ M22 _ RS XD1 RS XD1 RS XD1 RS XD1 R S TXD1 CRS TXD1 CRS TXD1 TXD0 RVED RVED TXD0 CRS TXD1 C RS TXD1 C RS TXEN T XD0 G XEN XD0 XD1 XD1 A H J 1 2 M1_R M1_ C M2_T M2_ R M4_T M4_ R M6_T M6_ R M7_T M7_ R M9_T M9_ R M11_ M11 _ M12_ M12 _ M14_ M14 _ M13_ M15 _ RE SE RE SE RE SE RE SE RE SE RE SE RE SE XD0 RS XD0 XD0 XD0 XD0 XD0 XD0 XD0 XD0 XD0 XD0 TXD0 RXD0 TXD0 RXD0 TXD0 RXD0 RXD0 CRS RVED R VED RVED R VED RVED R VED RVED M1_ R M2_T M2_ R M4_T M4_ R M6_T M6_ R M7_T M7_ R M9_T M9_ R M11_ M11 _ M12_ M12 _ M14_ M14 _ RE SE M13 _ RE SE RE SE RE SE RE SE RE SE RE SE XD1 XEN XD1 XEN XD1 XEN XD1 XEN XD1 XEN XD1 TXEN RXD1 TXEN RXD1 TXEN RXD1 RVED T XEN RVED R VED RVED R VED RVED R VED 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 72 Zarlink Semiconductor Inc. Data Sheet 13.2 Ball - Signal Descriptions ZL50415 All pins are CMOS type; all Input Pins are 5 Volt tolerance; and all Output Pins are 3.3 CMOS drive. 13.2.1 Ball Signal Descriptions Ball No(s) Symbol I/O Description I2C Interface Note: Use I2C and Serial control interface to configure the system A24 A25 Serial Control Interface A26 B26 C25 Frame Buffer Interface D20, B21, D19, E19,D18, E18, D17, E17, D16, E16, D15, E15, D14, E14, D13, E13, D21, E21, A18, B18, C18, A17, B17, C17, A16, B16, C16, A15, B15, C15, A14, B14, D9, E9, D8, E8, D7, E7, D6, E6, D5, E5, D4, E4, D3, E3, D2, E2, A7, B7, A6, B6, C6, A5, B5, C5, A4, B4, C4, A3, B3, C3, B2, C2 C14, A13, B13, C13, A12, B12, C12, A11, B11, C11, D11, E11, A10, B10, D10, E10, A8, C7 B8 C1 C9 D12 LA_D[63:0] I/O-TS with pull up Frame Bank A- Data Bit [63:0] STROBE D0 AUTOFD Input with weak internal pull up Input Output with pull up Serial Strobe Pin Serial Data Input Serial Data Output (AutoFD) SCL SDA Output I/O-TS with pull up I2C Data Clock I2C Data I/O LA_A[20:3] Output Frame Bank A - Address Bit [20:3] LA_ADSC# LA_CLK LA_WE# LA_WE0# Output with pull up Output Output with pull up Output with pull up Frame Bank A Address Status Control Frame Bank A Clock Input Frame Bank A Write Chip Select for one layer SRAM application Frame Bank A Write Chip Select for lower layer of two layers SRAM application Frame Bank A Write Chip Select for upper layer of two layers SRAM application E12 LA_WE1# Output with pull up Zarlink Semiconductor Inc. 73 ZL50415 Ball No(s) C8 A9 Symbol LA_OE# LA_OE0# I/O Output with pull up Output with pull up Data Sheet Description Frame Bank A Read Chip Select for one layer SRAM application Frame Bank A Read Chip Select for lower layer of two layers SRAM application Frame Bank A Read Chip Select for upper layer of two layers SRAM application B9 LA_OE1# Output with pull up Fast Ethernet Access Ports [15:0] RMII R28 P28 M_MDC M_MDIO Output I/O-TS with pull up MII Management Data Clock - (Common for all MII Ports [15:0]) MII Management Data I/O - (Common for all MII Ports - [15:0])) Reference Input Clock Ports [15:0] - Receive Data Bit [1] R29 AF21, AJ19, AF18, AJ17, AJ15, AF15, AJ13, AF12, AJ11, AJ9, AF9, AJ7, AF6, AJ5, AJ3, AF1 AE21, AH19, AH20, AH17, AH15, AE15, AH13, AE12, AH11, AH9, AE9, AH7, AE6, AH5, AH2, AF2 AH21, AF19, AF17, AG17, AG15, AF14, AG13, AF11, AG11, AG9, AF8, AG7, AF5, AG5, AH3, AF3 AE20, AJ18, AJ21, AJ16, AJ14, AE14, AJ12, AE11, AJ10, AJ8, AE8, AJ6, AE5, AJ4, AG1, AE1 AE18, AG18, AE16, AG16, AG14, AE13, AG12, AE10, AG10, AG8, AE7, AG6, AE4, AG4, AG3, AE3 AG19, AH18, AF16, AH16, AH14, AF13, AH12, AF10, AH10, AH8, AF7, AH6, AF4, AH4, AG2, AE2 LED Interface 74 M_CLKI M[15:0]_RXD[1] Input Input with weak internal pull up resistors. M[15:0]_RXD[0] Input with weak internal pull up resistors Ports [15:0] - Receive Data Bit [0] M[15:0]_CRS_DV Input with weak internal pull down resistors. Ports [15:0] - Carrier Sense and Receive Data Valid M[15:0]_TXEN I/O- TS with pull up, slew Ports [15:0] - Transmit Enable Strap option for RMII/GPSI M[15:0]_TXD[1] Output, slew Ports [15:0] - Transmit Data Bit [1] M[15:0]_TXD[0] Output, slew Ports [15:0] - Transmit Data Bit [0] Zarlink Semiconductor Inc. Data Sheet Ball No(s) C29 D29 E29 C27 D27 C26 D26 D25 D24 E24 Trunk Enable C22 TRUNK0 Input w/ weak internal pull down resistors Input w/ weak internal pull down resistors Trunk Port Enable Symbol LED_CLK/TSTOUT0 LED_SYN/TSTOUT1 LED_BIT/TSTOUT2 INIT_DONE/TSTOUT9 INIT_START/TSTOUT1 0 CHECKSUM_OK/TSTO UT11 FCB_ERR/TSTOUT12 MCT_ERR/TSTOUT13 BIST_IN_PRC/TSTOUT 14 BIST_DONE/TSTOUT1 5 I/O I/O- TS with pull up I/O- TS with pull up I/O- TS with pull up I/O- TS with pull up I/O- TS with pull up I/O- TS with pull up I/O- TS with pull up I/O- TS with pull up I/O- TS with pull up I/O- TS with pull up ZL50415 Description LED Serial Interface Output Clock LED Output Data Stream Envelope LED Serial Data Output Stream System start operation Start initialization EEPROM read OK FCB memory self test fail MCT memory self test fail Processing memory self test Memory self test done A21 TRUNK1 Trunk Port Enable Test Facility U3 T_MODE0 I/O-TS Test Pin - Set Mode upon Reset, and provides NAND Tree test output during test mode (Pull Up) Test Pin - Set Mode upon Reset, and provides NAND Tree test output during test mode (Pull Up) T_MODE1 T_MODE0 0 0 NandTree 0 1 Reserved 1 0 reserved 1 1 Regular operation T_MODE0 and T_MODE1 are used for manufacturing tests. The signals should both be set to 1 for regular operation. Scan Enable 0 - Normal mode (unconnected) C10 T_MODE1 I/O-TS F3 SCAN_EN Input with pull down Zarlink Semiconductor Inc. 75 ZL50415 Ball No(s) E27 Symbol SCANMODE I/O Input with pull down Data Sheet Description 1 - Enables Test mode. 0 - Normal mode (unconnected) System Clock, Power, and Ground Pins E1 K12, K13, K17,K18 M10, N10, M20, N20, U10, V10, U20, V20, Y12, Y13, Y17, Y18 F13, F14, F15, F16, F17, N6, P6, R6, T6, U6, N24, P24, R24, T24, U24, AD13, AD14, AD15, AD16, AD17 M12, M13, M14, M15, M16, M17, M18, N12, N13, N14, N15, N16, N17, N18, P12, P13, P14, P15, P16, P17, P18, R12, R13, R14, R15, R16, R17, R18, T12, T13, T14, T15, T16, T17, T18, U12, U13, U14, U15, U16, U17, U18, V12, V13, V14, V15, V16, V17, V18, F1 D1 Misc. D22 D23 E23 F2 G2 SCANCOL SCANCLK SCANLINK RESIN# RESETOUT_ Input Input/ output Input Input Output Scans the Collision signal of Home PHY Clock for scanning Home PHY collision and link Link up signal from Home PHY Reset Input Reset PHY SCLK VDD Input Power System Clock at 100 MHz +2.5 Volt DC Supply VCC Power +3.3 Volt DC Supply VSS Power Ground Ground AVCC AGND Analog Power Analog Ground Analog +2.5 Volt DC Supply Analog Ground 76 Zarlink Semiconductor Inc. Data Sheet Ball No(s) B22, A22, C23, B23, A23, C24, F4, F5, G4, G5, H4, H5, J4, J5, K4, K5, L4, L5, M4, M5, N4, N5, G3, H1, H2, H3, J1, J2, J3, K1, K2, K3, L1, L2, L3, M1, M2, M3, U4, U5, V4, V5, W4, W5, Y4, Y5, AA4, AA5, AB4, AB5, AC4, AC5, AD4, AD5, W1, Y1, Y2, Y3, AA1, AA2, AA3, AB1, AB2, AB3, AC1, AC2, AC3, AD1, AD2, AD3, N3, N2, N1, P3, P2, P1, R5, R4, R3, R2, R1, T5, T4, T3, T2, T1, W3, W2, V1, G1, V3, P4, P5, V2, U1, U2, U26, U25, V26, V25, W26, W25, Y27, Y26, AA26, AA25, AB26, AB25, AC26, AC25, AD26, AD25, T28, U28, R25, U29, T29, U27, V29, V28, V27, W29, W28, W27, Y29, Y28, Y25, AA29, AA28, AA27, AB29, AB28, AB27, T26, R26, T27, T25, P29, G26, G25, H26, H25, J26, J25, K25, K26, M25, L26, M26, L25, N26, N25, P26, P25, F28, G28, E25, G29, F29, G27,H29, H28, H27, J29, J28, J27, K29, K28, K27, L29, L28, L27, M29, M28, M27, F26, E26, F27, F25, N29,B24, AC29, AE28, AJ27, AF27,AJ25,AF24,AH23, AE19,AC28, AF28, AH27, AE27, AH25, AE24, AF22, AF20, AC27, AF29, AG27, AF26, AG25, AG23, AF23, AG21, AD29, AG28, AJ26, AE26, AJ24, AE23, AJ22, AJ20, AD27, AH28, AG26, AE25, AG24, AE22, AJ23, AG20, AD28, AG29, AH26, AF25, AH24, AG22, AH22, AE17, E20, B25 Symbol Reserved I/O-TS I/O ZL50415 Description Reserved Pin Zarlink Semiconductor Inc. 77 ZL50415 Ball No(s) Symbol I/O Data Sheet Description Bootstrap Pins (Default= pull up, 1= pull up 0= pull down) After reset TSTOUT0 to TSTOUT15 are used by the LED interface. C29 D29 TSTOUT0 TSTOUT1 Default: Enable (1) Reserved RMII MAC Power Saving Enable 0 - No power saving 1 - Power saving Reserved Default: SCLK (1) Scan Speed 0 - SCLK(HPNA) 1 - SCLK Reserved Default: 128K x 32 or 128K x 64 (1) Memory Size 0 - 256K x 32 or 256K x 64 (4M total) 1 - 128K x 32 or 128K x 64 (2M total) EEPROM Installed 0 - EEPROM installed 1 - EEPROM not installed MCT Aging 0 - MCT aging disable 1 - MCT aging enable FCB Aging 0 - FCB aging disable 1 - FCB aging enable Timeout Reset 0 - Time out reset disable 1 - Time out reset enable. Issue reset if any state machine did not go back to idle for 5 Sec. Reserved Default: Single depth (1) FDB RAM depth (1 or 2 layers) 0 - Two layers 1 - One layer Reserved. Default: Normal operation Default: RMII SRAM Test Mode 0 - Enable test mode 1 - Normal operation 0 - GPSI 1 - RMII C28, B28, E29 D28 TSTOUT[4:2] TSTOUT5 E28 A27 TSTOUT6 TSTOUT7 B27 TSTOUT8 Default: Not Installed (1) Default: MCT aging enable (1) Default: FCB aging enable (1) Default: Timeout reset enable (1) C27 TSTOUT9 D27 TSTOUT10 C26 TSTOUT11 D26 D25 TSTOUT12 TSTOUT13 D24 E24 TSTOUT14 TSTOUT15 AE20, AJ18, AJ21, AJ16, AJ14, AE14, AJ12, AE11, AJ10, AJ8, AE8, AJ6, AE5, AJ4, AG1, AE1, M[15:0]_TXEN 78 Zarlink Semiconductor Inc. Data Sheet Ball No(s) C21 C19, B19, A19 P_D OE_CLK[2:0] Symbol I/O Must be pulleddown Default: 111 ZL50415 Description Reserved - Must be pulled-down Programmable delay for internal OE_CLK from SCLK input. The OE_CLK is used for generating the OE0 and OE1 signals Suggested value is 001. Programmable delay for LA_CLK from internal OE_CLK. The LA_CLK delay from SCLK is the sum of the delay programmed in here and the delay in P_D[15:13]. Suggested value is 011. C20, B20, A20 LA_CLK[2:0] Default: 111 Notes: #= Input = In-ST = Output = Active low signal Input signal Input signal with Schmitt-Trigger Output signal (Tri-State driver) Out-OD= I/O-TS = I/O-OD = Output signal with Open-Drain driver Input & Output signal with Tri-State driver Input & Output signal with Open-Drain driver 13.3 Ball - Signal Name Signal Name LA_D[63] LA_D[62] LA_D[61] LA_D[60] LA_D[59] LA_D[58] LA_D[57] LA_D[56] LA_D[55] LA_D[54] LA_D[53] Ball No. D3 E3 D2 E2 A7 B7 A6 B6 C6 A5 B5 Signal Name LA_D[19] LA_D[18] LA_D[17] LA_D[16] LA_D[15] LA_D[14] LA_D[13] LA_D[12] LA_D[11] LA_D[10] LA_D[9] Ball No. A9 B9 F4 F5 G4 G5 H4 H5 J4 J5 K4 Signal Name LA_OE0# LA_OE1# RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED Ball No. D20 B21 D19 E19 D18 E18 D17 E17 D16 E16 D15 Zarlink Semiconductor Inc. 79 ZL50415 Ball No. E15 D14 E14 D13 E13 D21 E21 A18 B18 C18 A17 B17 C17 A16 B16 C16 A15 B15 C15 A14 B14 D9 E9 D8 E8 D7 E7 D6 E6 D5 E5 D4 Signal Name LA_D[52] LA_D[51] LA_D[50] LA_D[49] LA_D[48] LA_D[47] LA_D[46] LA_D[45] LA_D[44] LA_D[43] LA_D[42] LA_D[41] LA_D[40] LA_D[39] LA_D[38] LA_D[37] LA_D[36] LA_D[35] LA_D[34] LA_D[33] LA_D[32] LA_D[31] LA_D[30] LA_D[29] LA_D[28] LA_D[27] LA_D[26] LA_D[25] LA_D[24] LA_D[23] LA_D[22] LA_D[21] Ball No. C5 A4 B4 C4 A3 B3 C3 B2 C2 C14 A13 B13 C13 A12 B12 C12 A11 B11 C11 D11 E11 A10 B10 D10 E10 A8 C7 B8 C1 C9 D12 E12 Signal Name LA_D[8] LA_D[7] LA_D[6] LA_D[5] LA_D[4] LA_D[3] LA_D[2] LA_D[1] LA_D[0] LA_A[20] LA_A[19] LA_A[18] LA_A[17] LA_A[16] LA_A[15] LA_A[14] LA_A[13] LA_A[12] LA_A[11] LA_A[10] LA_A[9] LA_A[8] LA_A[7] LA_A[6] LA_A[5] LA_A[4] LA_A[3] LA_DSC# LA_CLK LA_WE# LA_WE0# LA_WE1# Ball No. K5 L4 L5 M4 M5 N4 N5 G3 H1 H2 H3 J1 J2 J3 K1 K2 K3 L1 L2 L3 M1 M2 M3 U4 U5 V4 V5 W4 W5 Y4 Y5 AA4 Data Sheet Signal Name RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED 80 Zarlink Semiconductor Inc. Data Sheet Ball No. E4 AB4 AB5 AC4 AC5 AD4 AD5 W1 Y1 Y2 Y3 AA1 AA2 AA3 AB1 AB2 AB3 AC1 AC2 AC3 AD1 AD2 AD3 N3 N2 N1 P3 P2 P1 R5 R4 R3 Signal Name LA_D[20] RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED Ball No. C8 U2 R28 P28 R29 AC29 AE28 AJ27 AF27 AJ25 AF24 AH23 AE19 AF21 AJ19 AF18 AJ17 AJ15 AF15 AJ13 AF12 AJ11 AJ9 AF9 AJ7 AF6 AJ5 AJ3 AF1 AC28 AF28 AH27 Signal Name LA_OE# RESERVED MDC MDIO M_CLK RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED M[15]_RXD[1] M[14]_RXD[1] M[13]_RXD[1] M[12]_RXD[1] M[11]_RXD[1] M[10]_RXD[1] M[9]_RXD[1] M[8]_RXD[1] M[7]_RXD[1] M[6]_RXD[1] M[5]_RXD[1] M[4]_RXD[1] M[3]_RXD[1] M[2]_RXD[1] M[1]_RXD[1] M[0]_RXD[1] RESERVED RESERVED RESERVED Ball No. AA5 AH7 AE6 AH5 AH2 AF2 AC27 AF29 AG27 AF26 AG25 AG23 AF23 AG21 AH21 AF19 AF17 AG17 AG15 AF14 AG13 AF11 AG11 AG9 AF8 AG7 AF5 AG5 AH3 AF3 AD29 AG28 ZL50415 Signal Name RESERVED M[4]_RXD[0] M[3]_RXD[0] M[2]_RXD[0] M[1]_RXD[0] M[0]_RXD[0] RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED M[15]_CRS_DV M[14]_CRS_DV M[13]_CRS_DV M[12]_CRS_DV M[11]_CRS_DV M[10]_CRS_DV M[9]_CRS_DV M[8]_CRS_DV M[7]_CRS_DV M[6]_CRS_DV M[5]_CRS_DV M[4]_CRS_DV M[3]_CRS_DV M[2]_CRS_DV M[1]_CRS_DV M[0]_CRS_DV RESERVED RESERVED Zarlink Semiconductor Inc. 81 ZL50415 Ball No. R2 R1 T5 T4 T3 T2 T1 W3 W2 V1 G1 V3 P4 P5 V2 U1 AE8 AJ6 AE5 AJ4 AG1 AE1 AD27 AH28 AG26 AE25 AG24 AE22 AJ23 AG20 AE18 AG18 Signal Name RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED M[5]_TXEN M[4]_TXEN M[3]_TXEN M[2]_TXEN M[1]_TXEN M[0]_TXEN RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED M[15]_TXD[1] M[14]_TXD[1] Ball No. AE27 AH25 AE24 AF22 AF20 AE21 AH19 AH20 AH17 AH15 AE15 AH13 AE12 AH11 AH9 AE9 AH8 AF7 AH6 AF4 AH4 AG2 AE2 U26 U25 V26 V25 W26 W25 Y27 Y26 AA26 Signal Name RESERVED RESERVED RESERVED RESERVED RESERVED M[15]_RXD[0] M[14]_RXD[0] M[13]_RXD[0] M[12]_RXD[0] M[11]_RXD[0] M[10]_RXD[0] M[9]_RXD[0] M[8]_RXD[0] M[7]_RXD[0] M[6]_RXD[0] M[5]_RXD[0] M[6]_TXD[0] M[5]_TXD[0] M[4]_TXD[0] M[3]_TXD[0] M[2]_TXD[0] M[1]_TXD[0] M[0]_TXD[0] RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED Ball No. AJ26 AE26 AJ24 AE23 AJ22 AJ20 AE20 AJ18 AJ21 AJ16 AJ14 AE14 AJ12 AE11 AJ10 AJ8 G27 H29 H28 H27 J29 J28 J27 K29 K28 K27 L29 L28 L27 M29 M28 M27 Data Sheet Signal Name RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED M[15]_TXEN M[14]_TXEN M[13]_TXEN M[12]_TXEN M[11]_TXEN M[10]_TXEN M[9]_TXEN M[8]_TXEN M[7]_TXEN M[6]_TXEN RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED 82 Zarlink Semiconductor Inc. Data Sheet Ball No. AE16 AG16 AG14 AE13 AG12 AE10 AG10 AG8 AE7 AG6 AE4 AG4 AG3 AE3 AD28 AG29 AH26 AF25 AH24 AG22 AH22 AE17 AG19 AH18 AF16 AH16 AH14 AF13 AH12 AF10 AH10 Signal Name M[13]_TXD[1] M[12]_TXD[1] M[11]_TXD[1] M[10]_TXD[1] M[9]_TXD[1] M[8]_TXD[1] M[7]_TXD[1] M[6]_TXD[1] M[5]_TXD[1] M[4]_TXD[1] M[3]_TXD[1] M[2]_TXD[1] M[1]_TXD[1] M[0]_TXD[1] RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED M[15]_TXD[0] M[14]_TXD[0] M[13]_TXD[0] M[12]_TXD[0] M[11]_TXD[0] M[10]_TXD[0] M[9]_TXD[0] M[8]_TXD[0] M[7]_TXD[0] Ball No. AA25 AB26 AB25 AC26 AC25 AD26 AD25 U27 V29 V28 V27 W29 W28 W27 Y29 Y28 Y25 AA29 AA28 AA27 AB29 AB28 AB27 R26 T25 T26 T28 U28 R25 U29 T29 Signal Name RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED Ball No. G26 G25 H26 H25 J26 J25 K25 K26 M25 L26 M26 L25 N26 N25 P26 P25 F28 G28 E25 G29 F29 F26 E26 F25 E24 D24 D25 D26 C26 D27 C27 ZL50415 Signal Name RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED BIST_DONE/TSTOUT[15] BIST_IN_PRC/TST0UT[14] MCT_ERR/TSTOUT[13] FCB_ERR/TSTOUT[12] CHECKSUM_OK/TSTOUT [11] INIT_START/TSTOUT[10] INIT_DONE/TSTOUT[9] Zarlink Semiconductor Inc. 83 ZL50415 Ball No. B27 A27 E28 D28 C28 B28 E29 D29 C29 N29 P29 F3 E1 U3 C10 B24 A21 C22 A26 B26 C25 A24 A25 F1 D1 D22 E23 E27 N28 N27 F2 G2 RESIN# RESETOUT_ Signal Name TSTOUT[8] TSTOUT[7] TSTOUT[6] TSTOUT[5] TSTOUT[4] TSTOUT[3] LED_BIT/TSTOUT[2] LED_SYN/TSTOUT[1] LED_CLK/TSTOUT[0] RESERVED RESERVED SCAN_EN SCLK T_MODE0 T_MODE1 RESERVED TRUNK1 TRUNK0 STROBE D0 AUTOFD SCL SDA AVCC AGND SCANCOL SCANLINK SCANMODE Ball No. U18 V12 V13 V14 V15 V16 V17 V18 N14 N15 N16 N17 N18 P12 P13 P14 P15 P16 C19 B19 A19 R13 R14 R15 R16 R17 R18 T12 T13 T14 T15 T16 Signal Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS OE_CLK2 OE_CLK1 OE_CLK0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Ball No. N12 N13 K17 K18 M10 N10 M20 N20 U10 V10 U20 V20 Y12 Y13 Y17 Y18 K12 K13 M16 M17 M18 F16 F17 N6 P6 R6 T6 U6 N24 P24 R24 T24 VSS VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS VSS VSS VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 Data Sheet Signal Name 84 Zarlink Semiconductor Inc. Data Sheet Ball No. B22 A22 C23 B23 A23 C24 D23 T27 F27 C20 B20 A20 C21 E20 B25 Signal Name Reserved Reserved Reserved Reserved Reserved RESERVED SCANCLK RESERVED RESERVED LA_CLK2 LA_CLK1 LA_CLK0 P_D RESERVED RESERVED Ball No. T17 T18 U12 U13 U14 U15 U16 U17 M12 M13 M14 M15 P17 P18 R12 Signal Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Ball No. U24 AD13 AD14 AD15 AD16 AD17 F13 F14 F15 ZL50415 Signal Name VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 13.4 13.4.1 AC/DC Timing Absolute Maximum Ratings -65C to +150C -40C to 85C +3.0 V to +3.6 V +2.38 V to +2.75 V -0.5 V to (VDD33 + 0.3 V) Storage Temperature Operating Temperature Supply Voltage VCC with Respect to VSS Supply Voltage VDD with Respect to VSS Voltage on Input Pins Caution: Stress above those listed may damage the device. Exposure to the Absolute Maximum Ratings for extended periods may affect device reliability. Functionality at or above these limits is not implied. 13.4.2 DC Electrical Characteristics TAMBIENT = -40C to 85C VCC = 3.0 V to 3.6 V (3.3v +/- 10%) VDD = 2.5V +10% - 5% Zarlink Semiconductor Inc. 85 ZL50415 13.4.3 Recommended Operation Conditions Preliminary Symbol fosc IDD1 IDD2 VOH VOL VIH-TTL VIL-TTL CIN COUT CI/O ja ja ja Data Sheet Parameter Description Min Frequency of Operation Supply Current - @ 100 MHz (VDD33=3.3 V) Supply Current - @ 100 MHz (VDD=2.5 V) Output High Voltage (CMOS) Output Low Voltage (CMOS) Input High Voltage (TTL 5V tolerant) Input Low Voltage (TTL 5V tolerant) Input Capacitance Output Capacitance I/O Capacitance Thermal resistance with 0 air flow Thermal resistance with 1 m/s air flow Thermal resistance with 2 m/s air flow VDD33 x 70% VDD33 - 0.5 0.5 VDD33 + 2.0 VDD33 x 30% 5 5 7 11.2 10.2 8.9 Typ 100 450 1500 Max Unit MHz mA mA V V V V pF pF pF C/W C/W C/W 86 Zarlink Semiconductor Inc. Data Sheet 13.5 13.5.1 Local Frame Buffer SBRAM Memory Interface Local SBRAM Memory Interface ZL50415 LA_CLK L1 L2 LA_D[63:0] Figure 12 - Local Memory Interface - Input setup and hold timing LA_CLK L3-max L3-min LA_D[63:0] L4-max L4-min LA_A[20:3] L6-max L6-min LA_ADSC# L7-max L7-min LA_WE[1:0]# #### L8-max L8-min LA_OE[1:0]# L9-max L9-min LA_WE# L10-max L10-min LA_OE# Figure 13 - Local Memory Interface - Output valid delay timing -100MHz Symbol L1 L2 L3 L4 L6 L7 Parameter LA_D[63:0] input set-up time LA_D[63:0] input hold time LA_D[63:0] output valid delay LA_A[20:3] output valid delay LA_ADSC# output valid delay LA_WE[1:0]#output valid delay Min (ns) 4 1.5 1.5 2 1 1 7 7 7 7 CL = 25pf CL = 30pf CL = 30pf CL = 25pf 87 Max (ns) Note: Zarlink Semiconductor Inc. ZL50415 L8 L9 L10 LA_OE[1:0]# output valid delay LA_WE# output valid delay LA_OE# output valid delay -1 1 1 1 7 5 CL = 25pf CL = 25pf CL = 25pf Data Sheet Table 10 - AC Characteristics - Local frame buffer SBRAM Memory Interface 13.6 13.6.1 AC Characteristics Reduced Media Independent Interface M_CLKI M6-max M6-min M[15:0]_TXEN M7-max M7-min M[15:0] _TXD[1:0] Figure 14 - AC Characteristics - Reduced media independent Interface M_CLKI M2 M[15:0]_RXD M3 M[15:0]_CRS_DV M4 M5 Figure 15 - AC Characteristics - Reduced Media Independent Interface -50MHz Symbol M2 M3 M4 M5 M6 M7 Parameter M[15:0]_RXD[1:0] Input Setup Time M[15:0]_RXD[1:0] Input Hold Time M[15:0]_CRS_DV Input Setup Time M[15:0]_CRS_DV Input Hold Time M[15:0]_TXEN Output Delay Time M[15:0]_TXD[1:0] Output Delay Time 4 1 4 1 2 2 11 11 CL = 20 pF CL = 20 pF Min (ns) Max (ns) Note: Table 11 - AC Characteristics - Reduced Media Independent Interface 88 Zarlink Semiconductor Inc. Data Sheet 13.6.2 LED Interface LED_CLK LE5-max LE5-min ZL50415 LED_SYN LE6-max LE6-min LED_BIT Figure 16 - AC Characteristics - LED Interface Variable FREQ. Symbol Parameter LED_SYN Output Valid Delay LED_BIT Output Valid Delay Min (ns) -1 -1 Max (ns) 7 7 Note: CL = 30pf CL = 30pf LE5 LE6 Table 12 - AC Characteristics - LED Interface 13.6.3 SCANLINK SCANCOL Output Delay Timing SCANCLK C5-max C5-min SCANLINK C7-max C7-min SCANCOL Figure 17 - SCANLINK SCANCOL Output Delay Timing SCANCLK C1 C2 SCANLINK C3 C4 SCANCOL Figure 18 - SCANLINK, SCANCOL Setup Timing Zarlink Semiconductor Inc. 89 ZL50415 -25MHz Symbol C1 C2 C3 C4 C5 C7 Parameter SCANLINK input set-up time SCANLINK input hold time SCANCOL input setup time SCANCOL input hold time SCANLINK output valid delay SCANCOL output valid delay Min (ns) 20 2 20 1 0 0 10 10 CL = 30pf CL = 30pf Max (ns) Data Sheet Note: Table 13 - SCANLINK, SCANCOL Timing 13.6.4 MDIO Input Setup and Hold Timing MDC D1 D2 MDIO Figure 19 - MDIO Input Setup and Hold Timing MDC D3-max D3-min MDIO Figure 20 - MDIO Output Delay Timing 1MHz Symbol D1 D2 D3 Parameter MDIO input setup time MDIO input hold time MDIO output delay time Min (ns) 10 2 1 Table 14 - MDIO Timing 20 CL = 50pf Max (ns) Note: 90 Zarlink Semiconductor Inc. Data Sheet 13.6.5 I2C Input Setup Timing SCL S1 S2 ZL50415 SDA Figure 21 - I2C Input Setup Timing SCL S3-max S3-min SDA Figure 22 - I 2C Output Delay Timing 50KHz Symbol S1 S2 S3* Parameter SDA input setup time SDA input hold time SDA output delay time Min (ns) 20 1 4 usec 6 usec CL = 30pf Max (ns) Note: * Open Drain Output. Low to High transistor is controlled by external pullup resistor. Table 15 - I 2 C Timing Zarlink Semiconductor Inc. 91 ZL50415 13.6.6 Serial Interface Setup Timing Data Sheet STROBE D1 D2 D4 D1 D2 D5 D0 Figure 23 - Serial Interface Setup Timing STROBE D3-max D3-min AutoFd Figure 24 - Serial Interface Output Delay Timing Symbol D1 D2 D3 D4 D5 D0 setup time D0 hold time Parameter Min (ns) 20 3s 1 5s 5s Max (ns) Note: AutoFd output delay time Strobe low time Strobe high time 50 CL = 100pf Table 16 - Serial Interface Timing 92 Zarlink Semiconductor Inc. E1 E DIMENSION A A1 A2 D D1 E E1 b e MIN MAX 2.20 2.46 0.50 0.70 1.17 REF 37.70 37.30 34.50 REF 37.70 37.30 34.50 REF 0.60 0.90 1.27 553 Conforms to JEDEC MS - 034 e D D1 A2 b NOTE: 1. CONTROLLING DIMENSIONS ARE IN MM 2. DIMENSION "b" IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER 3. SEATING PLANE IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 4. N IS THE NUMBER OF SOLDER BALLS 5. NOT TO SCALE. 6. SUBSTRATE THICKNESS IS 0.56 MM Package Code ISSUE ACN DATE APPRD. Previous package codes: For more information about all Zarlink products visit our Web Site at www.zarlink.com Information relating to products and services furnished herein by Zarlink Semiconductor Inc. trading as Zarlink Semiconductor or its subsidiaries (collectively "Zarlink") is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink. This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink's conditions of sale which are available on request. Purchase of Zarlink's I2C components conveys a licence under the Philips I2C Patent rights to use these components in an I2C System, provided that the system conforms to the I2C Standard Specification as defined by Philips. Zarlink and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2002, Zarlink Semiconductor Inc. All Rights Reserved. TECHNICAL DOCUMENTATION - NOT FOR RESALE |
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